Error correction trellis coding with periodically inserted known symbols
View Patent ↗The present invention discloses a system and method for channel coding data within a digital communication system. A data receiving circuit receives a digital input data sequence and periodically inserts known symbols, such as zeros, into the digital input data sequence as part of a convolutional zero code of the present invention. It forms an expanded digital input data sequence. An encoder is operatively connected to the data receiving circuit and trellis encodes the expanded sequence to produce a channel coded data stream such that the number of connections between trellis nodes in a trellis are reduced.
1. A system for channel coding data within a digital communications system comprising:
a data receiving circuit for receiving a digital input data sequence and periodically inserting known symbols into the digital input data sequence and forming an expanded digital input data sequence based on a constraint length; and
an encoder operatively connected to said data receiving circuit for trellis encoding the expanded digital input data sequence to produce a channel coded data stream such that the number of connections between trellis nodes in a trellis are reduced, said encoder operative according to the constraint length, and wherein the topology of the trellis corresponds to memory length m, and the known symbols are inserted after each m symbols within the input data sequence.
2. A system according to claim 1 , wherein the known symbols that are inserted comprise zeros.
3. A system according to claim 1 , wherein said encoder comprises a convolutional encoder.
4. A system according to claim 1 , wherein the encoder applies code words that are one-to-one mappings of the distinct paths on a trellis to binary sequences.
5. A system according to claim 1 , and further comprising a Maximum Likelihood (ML) decoder for receiving and decoding the channel coded data stream.
6. A system according to claim 5 , wherein the Maximum Likelihood (ML) decoder comprises a Viterbi decoder.
7. A system for channel coding data within a digital communications system comprising:
a data receiving circuit for receiving a digital input data sequence and periodically inserting known symbols into the digital input data sequence and forming an expanded digital input data sequence based on a constraint length; and
an encoder operatively connected to said data receiving circuit for trellis encoding the expanded digital input data sequence to produce a channel coded data stream such that the number of connections between trellis nodes in a trellis are reduced, said encoder operative according to the constraint length, wherein the encoder is operative as a generator matrix having a constraint length k=m−1, wherein m corresponds to the memory length, and the code rate is R=1/1 such that the known symbols are inserted after each k−1 information bit.
8. A method of channel coding data in a digital communications system comprising the steps of:
receiving a digital input data sequence;
periodically inserting known symbols into the digital input data sequence and forming an expanded digital input data sequence based on a constraint length; and
trellis encoding the expanded digital input data sequence based on the constraint length to produce a channel coded data stream such that the number of connections between trellis nodes in a trellis are reduced, wherein the topology of the trellis corresponds to the memory length m, and further comprising the step of inserting a known symbol after each m symbols within the input data sequence.
9. A method according to claim 8 , wherein the step of inserting known symbols comprises the step of inserting zeros into the digital input data sequence.
10. A method according to claim 8 , and further comprising the step of applying code words that are one-to-one mappings of the distinct paths on a trellis to binary sequences.
11. A method according to claim 8 , and further comprising the step of decoding channel coded data stream within a maximum likelihood (ML) decoder.
12. A method according to claim 11 , and further comprising the step of decoding the channel coded data stream within a Viterbi decoder.
13. A method of channel coding data in a digital communications system comprising the steps of:
receiving a digital input data sequence;
periodically inserting known symbols into the digital input data sequence and forming an expanded digital input data sequence based on a constraint length k=m−1, wherein m corresponds to a memory length and a code rate is R=1/1, such that the known symbols are inserted after each k−1 information bit; and
trellis encoding the expanded digital input data sequence to produce a channel coded data stream, wherein the number of connections between trellis nodes in a trellis are reduced.
14. A method according to claim 13 , wherein the step of inserting known symbols comprises the step of inserting zeros into the digital input data sequence.
15. A method according to claim 13 , and further comprising the step of applying code words that are one-to-one mappings of the distinct paths on a trellis to binary sequences.
16. A method according to claim 13 , and further comprising the step of decoding channel coded data stream within a maximum likelihood (ML) decoder.
17. A method according to claim 16 , and further comprising the step of decoding the channel coded data stream within a Viterbi decoder.