IP Library Granted Patent US 6,596,563
Granted Patent Utility
US 6,596,563 · Confirmation No. 1952

METHOD FOR DOUBLE-LAYER IMPLEMENTATION OF METAL OPTIONS IN AN INTEGRATED CHIP FOR EFFICIENT SILICON DEBUG

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Code Description Pages PDF
2002-03-04 TRNA Transmittal of New Application 2 View
2002-03-04 A.PE Preliminary Amendment 2 View
2002-03-04 SPEC Specification 8 View
2002-03-04 CLM Claims 4 View
2002-03-04 ABST Abstract 1 View
2002-03-04 DRW Drawings-only black and white line drawings 2 View
2002-03-04 OATH Oath or Declaration filed 5 View
2002-03-04 LET. Miscellaneous Incoming Letter 1 View
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Quick Facts
Patent No.
US 6,596,563
App. No.
10/091,620
Filed
2002-03-04
Granted
2003-07-22
Pub. No.
US20020096774A1
Examiner
DANG, PHUC T
Art Unit
2818
PTA
-86 days