Semaphore management circuit

1. A circuit, comprising:

a register which stores therein a semaphore address;

a semaphore control circuit which asserts a control signal in response to a read access by a processor directed to the semaphore address, and negates the control signal in response to a write access by the processor directed to the semaphore address, and

a bus-arbitration control circuit which receives a signal indicative of a bus-arbitration request, the control signal, and a chip enable signal output from the processor, and

wherein other resources are prohibited from accessing the semaphore address when the control signal is asserted, and a right to use a bus given to the processor is not relinquished in response to the bus-arbitration request supplied from an external source during an asserted state of the control signal, and

said bus-arbitration control circuit operating not to assert a bus-arbitration-acknowledge signal in response to the bus-arbitration request signal regardless of a state of the chip enable signal when the control signal is in the asserted state, operating not to assert the bus-arbitration-acknowledge signal in response to the bus-arbitration request signal when the chip enable signal is in an asserted state and the control signal is in a negated state, and operating to assert the bus-arbitration-acknowledge signal in response to the bus-arbitration request signal when the chip enable signal is in a negated state and the control signal is in the negated state.

2. The circuit as claimed in claim 1 , further comprising a comparator which makes a comparison of an address output from the processor with the semaphore address stored in said register, and asserts a match signal when the comparison indicates a match, wherein said semaphore control circuit includes:

a circuit which sets the control signal to an asserted state in response to assertion of the match signal and an indication of a read operation by a read/write signal output from the processor; and

a circuit which resets the control signal to a negated state in response to the assertion of the match signal and an indication of a write operation by the read/write signal output from the processor.

3. A processor, comprising:

a processor core;

a register which stores therein a semaphore address;

a control circuit which asserts a control signal in response to a read access by said processor core directed to the semaphore address, and negates the control signal in response to a write access by said processor core directed to the semaphore address, and

a bus-arbitration control circuit which receives a signal indicative of a bus-arbitration request, the control signal, and a chip enable signal output from the processor, and

wherein other resources are prohibited from accessing the semaphore address when the control signal is asserted, and a right to use a bus given to the processor is not relinquished in response to the bus-arbitration request supplied from an external source during an asserted state of the control signal, and

said bus-arbitration control circuit operating not to assert a bus-arbitration-acknowledge signal in response to the bus-arbitration request signal regardless of a state of the chip enable signal when the control signal is in the asserted state, operating not to assert the bus-arbitration-acknowledge signal in response to the bus-arbitration request signal when the chip enable signal is in an asserted state and the control signal is in a negated state, and operating to assert the bus-arbitration-acknowledge signal in response to the bus-arbitration request signal when the chip enable signal is in a negated state and the control signal is in the negated state.

4. The processor as claimed in claim 3 , wherein said control circuit includes:

a comparator which makes a comparison of an address output from said processor core with the semaphore address stored in said register, and asserts a match signal when the comparison indicates a match;

a circuit which sets the control signal to an asserted state in response to assertion of the match signal and an indication of a read operation by a read/write signal output from said processor core; and

a circuit which resets the control signal to a negated state in response to the assertion of the match signal and an indication of a write operation by the read/write signal output from said processor core.

5. A multi-processor system, comprising:

a plurality of processors;

a memory shared by said plurality of processors;

a semaphore register for controlling exclusive use of said memory, wherein at least one of said plurality of processors includes:

a processor core;

an address register which stores therein an address of said semaphore register; and

a control circuit which asserts a control signal in response to a read access by said processor core directed to the address stored in said address register, and negates the control signal in response to a write access by said processor core directed to the address stored in said address resister; and

a bus-arbitration control circuit which receives a signal indicative of a bus-arbitration request, the control signal, and a chip enable signal output from the processor, and

wherein other resources are prohibited from accessing the semaphore address when the control signal is asserted, and a right to use a bus given to the processor is not relinquished in response to the bus-arbitration request supplied from an external source during an asserted state of the control signal, and

said bus-arbitration control circuit operating not to assert a bus-arbitration-acknowledge signal in response to the bus-arbitration request signal regardless of a state of the chip enable signal when the control signal is in the asserted state, operating not to assert the bus-arbitration-acknowledge signal in response to the bus-arbitration request signal when the chip enable signal is in an asserted state and the control signal is in a negated state, and operating to assert the bus-arbitration-acknowledge signal in response to the bus-arbitration request signal when the chip enable signal is in a negated stafe and the control signal is in the negated state.

6. The multi-processor system as claimed in claim 5 , wherein said control circuit includes:

a comparator which makes a comparison of an address output from said processor core with the semaphore address stored in said address register, and asserts a match signal when the comparison indicates a match;

a circuit which sets the control signal to an asserted state in response to assertion of the match signal and an indication of a read operation by a read/write signal output from said processor core; and

a circuit which resets the control signal to a negated state in response to the assertion of the match signal and an indication of a write operation by the read/write signal output from said processor core.

7. A method for controlling a semaphore in a system including at least one processor and a bus-arbitration control circuit, comprising: asserting a control signal when the processor performs a read access to a semaphore address;

said bus-arbitration control circuit receiving a signal indicative of a bus-arbitration request, the control signal, and a chip enable signal output from the processor;

negating the control signal when the processor performs a write access to the semaphore address, and a right to use a bus give to the processor is not relinquished in response to the bus arbitration request supplied from an external source during an asserted state of the control signal; and

said bus-arbitration control circuit operating not to assert a bus-arbitration-acknowledge signal in response to the bus-arbitration request signal regardless of a state of the chip enable signal when the control signal is in the asserted state, operating not to assert the bus-arbitration-acknowledge signal in response to the bus-arbitration request signal when the chip enable signal is in an asserted state and the control signal is in a negated state, and operating to assert the bus-arbitration-acknowledge signal in response to the bus-arbitration request signal when the chip enable signal is in a negated state and the control signal is in the negated state.

8. A circuit, comprising:

a register storing a semaphore address;

a bus-arbitration control circuit which receives a signal indicative of a bus-arbitration request, the control signal, and a chip enable signal output from the processor;

a semaphore control circuit which asserts a control signal in response to a read access by a processor directed to the semaphore address, and negates the control signal in response to a write access by the processor directed to the semaphore address, the control signal preventing other processors from accessing the semaphore address, and a right to use a bus given to the processor is not relinquished in response to a bus-arbitration request supplied from an external source during an asserted state of the control signal, and

where said bus-arbitration control circuit operating not to assert a bus-arbitration-acknowledge signal in response to the bus-arbitration request signal regardless of a state of the chip enable signal when the control signal is in the asserted state, operating not to assert the bus-arbitration-acknowledge signal in response to the bus-arbitration request signal when the chip enable signal is in an asserted state and the control signal is in a negated state, and operating to assert the bus-arbitration-acknowledge signal in response to the bus-arbitration request signal when the chip enable signal is in a negated state and the control signal is in the negated state.