Multidispatch CPU integrated circuit having virtualized and modular resources and adjustable dispatch priority
View Patent ↗A multiple dispatch processor has several instruction fetch units, each for providing a stream of instructions to an instruction decode and dispatch unit. The processor also has an resource allocation unit, and multiple resources such as combined integer and address execution pipelines and floating point execution pipelines. Each instruction decode and dispatch unit requests resources needed to perform an instruction of the resource allocation unit, which arbitrates among the multiple instruction decode and dispatch units.
1. A multiple dispatch processor comprising:
a plurality of instruction fetch units, each instruction fetch unit capable of fetching a stream of instructions;
a plurality of instruction decode and dispatch units each coupled to a corresponding instruction fetch unit of the plurality of instruction fetch units to receive instructions therefrom;
at least one register file coupled for storing operands;
a plurality of execution units coupled to the register file and to the instruction decode and dispatch units for performing operations on operands as directed by the plurality of instruction decode and dispatch units; and
a resource allocation unit coupled to allocate execution units among the instruction decode and dispatch units; and
wherein the plurality of execution units further comprises a plurality of multifunction execution units, each of the multifunction execution units capable of handling integer and address operations.
2. The multiple dispatch processor of claim 1 , wherein the plurality of execution units further comprises a plurality of floating point execution units.
3. A multiple dispatch processor comprising:
a plurality of instruction fetch units, each instruction fetch unit capable of fetching a stream of instructions;
a plurality of instruction decode and dispatch units each coupled to a corresponding instruction fetch unit of the plurality of instruction fetch units to receive instructions therefrom;
at least one register file coupled for storing operands;
a plurality of execution units coupled to the register file and to the instruction decode and dispatch units for performing operations on operands as directed by the plurality of instruction decode and dispatch units; and
a resource allocation unit coupled to allocate execution units among the instruction decode and dispatch units;
wherein at least a first execution unit has a clock signal turned off when the first execution unit is marked unavailable in the resource available register, and the clock signal is turned on when the first execution unit is marked available in the resource allocation register.
4. The multiple-dispatch processor of claim 3 wherein at least one execution unit is marked unavailable in the resource allocation register when the processor is operating under low power availability.
5. The multiple-dispatch processor of claim 3 wherein the execution units further comprise a plurality of address-and-integer units and a plurality of floating point units.