Data synchronization circuit and communication interface circuit
View Patent ↗There is provided a data synchronization circuit for synchronizing a (n+1) (n: natural number) bit bus data synchronous with a first clock with a second clock, comprising: a first circuit for holding the bus data which is synchronous with the first clock and is input at each predetermined timing; a second circuit for generating a first timing signal which is synchronous with the first clock and is corresponding to the predetermined timing; a third circuit for generating a second timing signal which is synchronous with the second clock, from the first timing signal; and a fourth circuit for receiving the bus data output from the first circuit based on the second timing signal, to output the bus data in synchronism with the second clock.
1. A data synchronization circuit for synchronizing a (n+1) (n: natural number) bit bus data synchronous with a first clock with a second clock, comprising:
a first circuit for holding the bus data which is synchronous with the first clock and is input at each predetermined timing;
a second circuit for generating a first timing signal which is synchronous with the first clock and is corresponding to the predetermined timing;
a third circuit for generating a second timing signal which is synchronous with the second clock, from the first timing signal; and
a fourth circuit for receiving the bus data output from the first circuit based on the second timing signal, to output the bus data in synchronism with the second clock.
2. A data synchronization circuit according to claim 1 , wherein
the third circuit includes a plurality of flip-flop circuits.
3. A communication interface circuit for transmitting and receiving a line data to be transmitted through a communication line, comprising:
a conversion circuit for converting the line data into (n+1) (n: natural number) bit bus data to be internally transferred and for converting the bus data into the line data; and
a data synchronization circuit for synchronizing the bus data synchronous with a first clock with a second clock, the data synchronization circuit including: a first circuit for holding the bus data which is synchronous with the first clock and is input at each predetermined timing;
a second circuit for generating a first timing signal which is synchronous with the first clock and is corresponding to the predetermined timing;
a third circuit for generating a second timing signal which is synchronous with the second clock, from the first timing signal; and
a fourth circuit for receiving the bus data output from the first circuit based on the second timing signal, to output the bus data in synchronism with the second clock.
4. A communication interface circuit according to claim 3 , wherein
the line data is a serial data.