Power-on reset circuit for use in low power supply voltage applications
View Patent ↗Systems and methods are disclosed for a power-on reset used in low power supply voltage applications (i.e., having a full operating power supply voltage of less than about 2.0 volts). One embodiment of the reset circuit comprises a differential voltage generation circuit and an amplifier circuit. The differential voltage generation circuit is adapted to create two voltages changing at different rates. The amplifier circuit is adapted to amplify a difference between the two voltages.
1. A reset circuit comprising:
a differential voltage generation circuit adapted to create two voltages changing at different rates forming a voltage difference, wherein said voltage difference increases with an increase in power supply voltage;
an amplifier circuit having at least one Schmidt trigger adapted to amplify a difference between said two voltages, thereby instructing a register to hold a predetermined state; and
a switch comprising two PMOS devices adapted to power down the reset circuit for testing.
2. The circuit of claim 1 , wherein said differential voltage generation circuit produces a varied rate voltage pair.
3. The circuit of claim 1 , wherein said differential voltage generation circuit comprises a resistor divider circuit.
4. The circuit of claim 3 , wherein said resistor divider circuit comprises at least one transistor.
5. The circuit of claim 4 , wherein said at least one transistor comprises at least one PMOS device.
6. The circuit of claim 3 , wherein said resistor divider circuit comprises two series resistors.
7. The circuit of claim 6 , wherein said two series resistors have different resistance values.
8. The circuit of claim 1 , wherein said amplifier circuit comprises at least one PMOS device.
9. The circuit of claim 1 , wherein said amplifier circuit comprises at least one NMOS device.
10. The circuit of claim 1 further comprising at least two transistor devices coupled to at least one of said differential voltage generation and amplifier circuits, wherein said transistor devices are adapted to be used with a secondary power supply.
11. The circuit of claim 1 , further comprising a hysteresis element adapted to prevent false re-triggering of the reset circuit.
12. The circuit of claim 11 , wherein said hysteresis element comprises a PMOS transistor.
13. The circuit of claim 1 , wherein said amplifier circuit comprises a first amplifier circuit and a second amplifier circuit comprising at least said Schmidt trigger, said second amplifier circuit coupled to at least said first amplifier circuit.
14. The circuit of claim 13 , wherein said second amplifier circuit comprising at least said Schmidt trigger is adapted to amplify an output of said first amplifier circuit.
15. The circuit of claim 1 , wherein the circuit is adapted to be used with primary and secondary power supplies.
16. The circuit of claim 15 , wherein said primary power supply comprises a low voltage power supply.
17. The circuit of claim 15 , wherein said secondary power supply comprises a high voltage power supply.
18. The circuit of claim 1 , wherein said amplifier circuit comprises at least a self-referenced amplifier.