PLL noise smoothing using dual-modulus interleaving
View Patent ↗The present invention, generally speaking, achieves noise spreading within a PLL using a dual-modulus prescaler by interleaving the division moduli. Within a given cycle, “ones” and “tens” are not all counted consecutively. Instead, ones and tens are interleaved. In one embodiment of the invention, the R count is doubled and the output of the R counter is toggled between high and low states. (The Q counter may remain unmodified.) In another embodiment of the invention, ones and tens are interleaved in accordance with a ratio q:r. By so interleaving the modulus, the effect is to spread the noise resulting from the output signal of the dual-modulus prescaler over a wider frequency range. The prescaler noise level is greatly reduced, particularly within the frequency band of the reference frequency.
1. A method of operating a frequency divider that performs frequency division of an applied signal by a factor N, which is an integer greater than or equal to one, to produce an output signal, the frequency divider including a multiple-modulus prescaler controlled by a modulus control signal, the method comprising:
causing the modulus control signal to transition greater than two times per period of the output signal to obtain division by N;
whereby noise energy produced by transitions of the modulus control signal is moved away from a frequency band of the output signal.
2. The method of claim 1 , further comprising:
deriving a reduced-frequency signal; and
toggling the modulus control signal in accordance with transitions of the reduced-frequency signal.
3. The method of claim 1 , further comprising:
distributing transitions of the modulus control signal occurring during one period of the output signal substantially evenly throughout that period of the output signal.
4. A frequency divider that performs division of an applied signal by a factor of N, which is greater than or equal to one, to produce an output signal, comprising:
a multiple-modulus prescaler controlled by a modulus control signal; and
a counter circuit coupled to the multiple-modulus prescaler and used to produce the modulus control signal, the counter circuit including control means for causing the modulus control signal to transition greater than two times per period of the output signal;
whereby noise energy produced by transitions of the modulus control signal is moved away from a frequency band of the output signal.
5. The frequency divider of claim 4 , wherein the multiple-modulus prescaler derives a reduced-frequency signal, said control means toggling the modulus control signal in accordance with transitions of the reduced-frequency signal.
6. The frequency divider of claim 4 , wherein said control means distributes transitions of the modulus control signal occurring during one period of the output signal substantially evenly throughout that period of the output signal.
7. A phase locked loop, comprising:
a phase detector having a first input configured to receive a reference frequency signal;
a voltage controlled oscillator (VCO) operable to produce an output frequency signal;
a loop filter disposed between an output of the phase detector and an input of the VCO; and
a frequency dividing circuit coupled between an output of the VCO and a second input of the phase detector, the frequency dividing circuit having:
a multiple-modulus prescaler;
a first counter coupled to the multi-modulus prescalar that counts R total counts r at a time;
a second counter coupled to the multi-modulus prescalar that counts Q total counts q at a time; and
a control circuit for repeatedly selecting in turn a first modulus for r counts and a second modulus for q counts,
wherein R, r, Q and q are integers and r is an integer that does not equal R.
8. A circuit, comprising:
a multi-modulus prescalar having a multi-modulus control input;
a first counter operable to divide a signal by a first modulus for a first period of time and generate a multi-modulus control signal that is coupled to the multi-modulus control input of the multi-modulus prescalar; and
a second counter operable to divide said signal by a second modulus for a second period time after said first period of time expires,
wherein said multi-modulus control signal is repeatedly toggled between high and low states during said first period of time.