IP Library Granted Patent US 6,957,292
Granted Patent B2
US 6,957,292 · App. 10/096,925 · Granted Oct 18, 2005

Universal Serial Bus circuit which detects connection status to a USB host

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Quick Facts
Patent No.
US 6,957,292
App. No.
10/096,925
Granted
Oct 18, 2005
Kind
B2
Abstract

The invention relates to universal serial bus circuits utilized in USB devices and USB hubs. Specifically, the invention relates to circuitry used to detect whether the hub or device is connected td a USB host, i.e. to detect connection status of the device or hub. The present invention provides a USB circuit comprising a microprocessor which receives signaling concerning the connection status of the USB circuit to a USB host circuit, first and second data signal lines which transmit respective first and second data signals to the microprocessor, a USB host power supply signal line which receives USB host power signaling to indicate connection status, and wherein the USB circuit analyzes the USB power supply signal line and change the data signal transmittal down the first and second data lines according to the connection statas of USB circuit to the USB host circuit.

Claims (45)

1. A USB circuit comprising:

a microprocessor which receives signaling concerning a connection status of the USB circuit to a USB host circuit;

first and second data signal lines which transmit respective first and second data signals to the microprocessor;

a USB host power supply signal line which receives USB host power signaling to indicate the connection status; and

wherein the USB circuit comprises connection status signaling means which analyze the USB power supply signal line and change the data signal transmitted down the first and second data lines according to the connection status of the USB circuit to the USB host circuit and simultaneously sends a “1” signal down each of the data lines to the microprocessor when the USB circuit is in a disconnected state.

2. The USB circuit according to claim 1 , wherein the connection status signaling means comprises a NOT gate and two OR gates, the NOT gate providing an input into each of the two OR gates, remaining OR gate inputs each being connected to the host end of one of the data signal lines, and wherein the output of the two OR gates is connected to a microprocessor end of the corresponding data line.

3. The USB circuit according to claim 2 , wherein the circuit includes a NAND gate connected to the data lines to convert the simultaneous “1” signaling state to a single “0” signal state.

4. The USB circuit according to claim 2 , comprising a signal filter which reduces signal inconsistencies between signaling from the data signal lines.

5. The USB circuit according to claim 1 , wherein the circuit includes a NAND gate connected to the data lines to convert the simultaneous “1” signaling state to a single “0” signal state.

6. The USB circuit according to claim 5 , comprising

a signal filter connected to the NAND gate input to reduce signal inconsistencies.

7. The USB circuit according to claim 6 , wherein the NAND gate incorporated into the microprocessor.

8. The USB circuit according to claim 5 , wherein the NAND gate is incorporated into the microprocessor.

9. The USB circuit according to claim 5 , comprising a signal filter which reduces signal inconsistencies between signaling from the data signal lines.

10. The USB circuit according to claim 1 , comprising a signal filter which reduces signal inconsistencies between signaling from the data signal lines.

11. The USB circuit according to claim 1 , comprising a signal filter which reduces signal inconsistencies between signalling from the data signal lines.

12. The USB circuit according to claim 11 , comprising a signal filter connected to the NAND gate input to reduce signal inconsistencies.

13. The USB circuit according to claim 11 , wherein the NAND gate incorporated into the microprocessor.

14. The USB circuit according to claim 1 , wherein the microprocessor and/or connection status signaling means is contained in a USB Digital ASIC.

15. The USB circuit according to claim 14 , wherein the USB circuit comprises a transceiver and the microprocessor is incorporated into the transceiver.

16. The USB circuit according to claim 1 , wherein the USB circuit comprises a transceiver and the connection status signaling means is incorporated into the transceiver.

17. The USB circuit according to claim 1 , wherein the USB circuit is incorporated into a USB device.

18. The USB circuit according to claim 1 , wherein the USB circuit is incorporated into a USB hub.

19. The USB circuit according to claim 1 comprising:

a USB device.

20. The USB circuit according to claim 1 comprising:

a USB hub.

21. The USB circuit according to claim 1 comprising:

a printer.

22. The USB circuit according to claim 1 comprising:

a keyboard.

23. The USB circuit according to claim 1 comprising:

a scanner.

24. The USB circuit according to claim 1 comprising:

a modem.

25. The USB circuit according to claim 1 comprising:

a camera.

26. The USB circuit according to claim 1 comprising:

a mobile telephone.

27. The USB circuit according to claim 1 comprising:

a MP3 player.

28. The USB circuit according to claim 1 comprising:

a device performing multiple functions.

29. The USB circuit according to claim 1 comprising:

a monitor.

Assignments (4)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Feb 8, 2019
From: III HOLDINGS 3, LLC
To: SEAGATE TECHNOLOGY LLC
Reel/Frame 048272/0476 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jan 29, 2019
From: III HOLDINGS 3, LLC
To: SEAGATE TECHNOLOGY LLC
Reel/Frame 048167/0929 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Feb 17, 2015
From: NOKIA CORPORATION
To: III HOLDINGS 3, LLC
Reel/Frame 034974/0644 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded May 8, 2002
From: CROYLE, RICHARD
To: NOKIA CORPORATION
Reel/Frame 012871/0237 →