Liquid crystal display apparatus operating at proper data supply timing
View Patent ↗A circuit for driving a liquid crystal display panel includes a plurality of output circuits that are coupled to respective data bus lines of the liquid crystal display panel, and output liquid crystal drive signals to the respective data bus lines with respective delays that progressively increase from a first one of the data bus lines to a last one of the data bus lines.
1. A circuit for driving a liquid crystal display panel, which is to be coupled to and supply display data to data bus lines of the liquid crystal display panel, comprising:
input nodes which receive the display data and a clock signal;
registers configured to store the display data as parallel data;
first output nodes which output the display data stored in said registers to the data bus lines;
a synchronizing circuit coupled to said registers to convert the display data stored in said registers into serial data synchronized with the clock signal; and
a second output node which supplies the serial data synchronized with the clock signal by said synchronizing circuit to a circuit for driving the liquid crystal display panel provided at a next stage.
2. The circuit as claimed in claim 1 , wherein said synchronizing circuit is a register circuit.
3. The circuit as claimed in claim 1 , further comprising:
a register circuit which synchronizes a cascade signal with the clock signal; and
a third output node which supplies the cascade signal synchronized with the clock signal by said register circuit to said circuit for driving the liquid crystal display panel provided at the next stage.
4. A liquid crystal display apparatus, comprising:
a liquid crystal display panel which includes data bus lines and gate bus lines;
a plurality of gate drivers which drive the gate bus lines; and
a plurality of data drivers which drive the data bus lines, wherein the data drivers are connected in a cascade connection, and at least one of the data drivers includes:
input nodes which receive display data and a clock signal;
registers configured to store the display data as parallel data;
first output nodes which output the display data stored in said registers to the data bus lines;
a synchronizing circuit coupled to said registers to convert the display data stored in said registers into serial data synchronized with the clock signal; and
a second output node which supplies the display data synchronized with the clock signal by said synchronizing circuit to a next one of the data drivers provided at a next stage.
5. The liquid crystal display apparatus as claimed in claim 4 , wherein at least one of said data drivers includes:
a register circuit which synchronizes a cascade signal with the clock signal; and
a third output node which supplies the cascade signal synchronized with the clock signal by said register circuit to a next one of the data drivers provided at a next stage.