Granted Patent
Utility
US 6,512,394
· Confirmation No. 5476
TECHNIQUE FOR EFFICIENT LOGIC POWER GATING WITH DATA RETENTION IN INTEGRATED CIRCUIT DEVICES
Inventor:
Michael C. Parris
Patented Case
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Code | Description | Pages | ||
|---|---|---|---|---|---|
| 2002-03-14 | TRNA |
Transmittal of New Application | 3 | View | |
| 2002-03-14 | SPEC |
Specification | 13 | View | |
| 2002-03-14 | CLM |
Claims | 5 | View | |
| 2002-03-14 | ABST |
Abstract | 1 | View | |
| 2002-03-14 | DRW |
Drawings-only black and white line drawings | 4 | View | |
| 2002-03-14 | OATH |
Oath or Declaration filed | 2 | View |
Inventors
Michael C. Parris
Colorado Springs, CO
Attorneys & Agents of Record
Classification
USPC
326/34
H03K19/00361
G05F3/24
Prosecution
- Examiner
- CHANG, DANIEL D
- Art Unit
- 2819
- Customer No.
- 25235
- Docket No.
- UMI-326
- Confirmation No.
- 5476
Patent Term Adjustment
0days
No related applications found.
from
PARRIS, MICHAEL C.
ASSIGNMENT OF ASSIGNOR'S INTEREST
Recorded 2002-03-14
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Quick Facts
- Patent No.
- US 6,512,394
- App. No.
- 10/098,872
- Filed
- 2002-03-14
- Granted
- 2003-01-28
- Examiner
- CHANG, DANIEL D
- Art Unit
- 2819
- PTA
- 0 days
External Links