IP Library Granted Patent US 7,216,342
Granted Patent B2
US 7,216,342 · App. 10/099,455 · Granted May 8, 2007

Code generation

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Quick Facts
Patent No.
US 7,216,342
App. No.
10/099,455
Granted
May 8, 2007
Kind
B2
Abstract

A method of linking a plurality of object files to generate an executable program, the method comprises identifying in the object files at least one routine to be locked into a cache when the program is executed, locating said routine at a set of memory addresses which man onto a set of cache locations and introducing into the executable program gaps at other sets of memory addresses which map onto the same set of cache locations.

Claims (20)

1. A method of linking a plurality of object files to generate an executable program, the method comprising:

identifying in the object files a routine to be locked into a cache when the program is executed;

locating said routine at a set of memory addresses which map onto a set of cache locations; and

introducing into the executable program a gap at another set of memory addresses which maps onto the set of cache locations.

2. A method according to claim 1 , wherein the step of introducing a gap into the executable program comprises locating other routines in said object files at sets of memory addresses which do not map onto the set of cache locations.

3. A method according to claim 1 , wherein the step of introducing a gap into the executable program comprises the step of splitting a routine to be located at a set of memory addresses which do not map onto the set of cache locations and which cannot be fitted into the cache otherwise.

4. A method according to claim 3 , wherein the step of splitting a routine includes the step of introducing a branch instruction at an end of a first part of the routine to identify a memory address of a second part of the routine.

5. A method according to claim 1 , wherein the routine is an interrupt handler routine.

6. A linker apparatus for linking a plurality of object files to generate an executable program, the linker comprising:

means for identifying in the object files a routine to be locked into a cache when the program is executed;

means for locating said routine at a set of memory addresses which maps onto a set of cache locations; and

means for introducing into the executable program a gap at another set of memory addresses which maps onto the set of cache locations.

7. A linker apparatus according to claim 6 , wherein the means for introducing a gap into the executable program comprises means for splitting a routine that is of too great a size to be fitted into the cache otherwise.

8. A linker apparatus according to claim 6 , which comprises a store for holding names of routines to be locked into a cache.

9. A linker apparatus according to claim 6 , which comprises means for creating a list of routines in the object files to be linked, said list including a locking status associated with each routine, the locking status indicating whether the routine is to be locked in the cache.

10. A computer program product comprising program code in the form of an executable program containing a plurality of routines, wherein at least one of said routines is located at a set of memory addresses which maps onto a set of cache locations and wherein another set of memory addresses which maps onto the set of cache locations the executable program contains a gap, whereby when the computer program product is loaded into a computer and executed, said at least one routine is locked into the cache.

11. The computer program product of claim 10 wherein the gap includes an empty memory address.

12. The method of claim 1 wherein the gap includes an empty memory address.

13. The method of claim 1 , wherein the identifying step includes creating a list of routines in the object files, said list including a locking status associated with each routine, the locking status indicating whether the routine is to be locked in the cache.

14. The linker of claim 6 wherein the gap includes an empty memory address.

Assignments (2)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded May 31, 2016
From: STMICROELECTRONICS LIMITED
To: STMICROELECTRONICS (RESEARCH & DEVELOPMENT) LIMITED
Reel/Frame 038847/0890 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jun 24, 2002
From: SOUTHWELL, TREFOR; HEDINGER, PETER
To: STMICROELECTRONICS LIMITED
Reel/Frame 013024/0395 →