Symmetric line coding
View Patent ↗A method an apparatus for symmetric line coding is provided where a binary input signal d is received; a value for each of a pair of binary bits p and q are dynamically defined in response to the input stream; and a pair of output bitstreams v 1 and v 2 are dynamically generated in accordance with the following: if d=1, then v 1 =p and v 2 =p, and if d=0, then v 1 =(1−q) and v 2 =q. In illustrative embodiments of the invention, the generation may be performed by symmetric-line coding machines, including: a bitstream symmetric line coding machine, a regular bitstream symmetric line coding machine, a complementary regular bitstream symmetric line coding machine, a binary complementary regular symmetric line coding machine, a bitstream parallel symmetric line coding machine, a regular bitstream parallel symmetric line coding machine, a complementary regular bitstream parallel symmetric line coding machine, and a binary complementary regular parallel symmetric line coding machine.
1. A method comprising the steps of:
receiving a binary input stream d;
dynamically defining the value for each of a pair of binary bits p and q in response to the binary input stream d; and
dynamically generating an output pair of bitstreams, v 1 and v 2 , where the generating is performed in accordance with the following
(a) for a binary input d of a value, then both v 1 and v 2 are supplied with same value of either binary bit p or binary bit q, and
(b) for a complement to the value of binary input d, then supply to the output pair, a value of an other binary bit p or q that was not supplied in step (a) and a complement to the other binary bit p or q.
2. A method comprising the steps of:
receiving a binary input stream d;
dynamically defining a value for each of a pair of binary bits p and q in response to the binary input stream d; and
dynamically generating the output pair of bitstreams as an output, v 1 and v 2 , where the generating is performed in accordance with the following
(a) if d=1, then v 1 =p and v 2 =qp, and
(b) if d=0, then v 1 =(1−q) and v 2 =q.
3. A symmetric line coding apparatus, comprising:
an input port for receiving a binary input signal d;
a circuit coupled to the input port to dynamically define a value for each of a pair of binary bits p and q in response to the binary input stream d;
a pair of output ports coupled to the circuit, whereby the circuit dynamically generates an pair of bitstreams, v 1 and v 2 , for output at the pair of outputs ports and the generating is performed in accordance with the following
(a) for a binary input d of a value, then both v 1 and v 2 are supplied with same value of either binary bit p or binary bit q, and
(b) for a complement to the value of binary input d, then supply to the output pair, a value of an other binary bit p or q that was not supplied in step (a) and a complement to the other binary bit p or q.
4. The apparatus of claim 3 further including a dual input modulator coupled to the respective output ports.
5. The apparatus of claim 4 whereby the modulator is a Mach-Zender modulator.
6. A symmetric line coding apparatus, comprising:
an input port for receiving a binary input signal d;
a circuit coupled to the input port to dynamically define a value for each of a pair of binary bits p and q in response to the binary input stream d;
a pair of output ports coupled to the circuit, whereby the circuit dynamically generates an pair of bitstreams, v 1 and v 2 , for output at the pair of outputs ports and the generating is performed in accordance with the following
(a) if d=1, then v 1 =p and v 2 =qp, and
(b) if d=0, then v 1 =(1−q) and v 2 =q.
7. The apparatus according to claim 6 further including a data latch coupled to the input port to latch the state of the input bit stream at each clock cycle.
8. The apparatus of claim 6 further including a switch coupled to each output port for selecting the value of an output bitstream supplied at each the output ports.
9. A symmetric line coding apparatus, comprising:
an input port for receiving a binary input signal d;
a circuit coupled to the input port to dynamically define a value for each of a pair of binary bits p and q in response to the binary input stream d;
a pair of output ports coupled to the circuit, whereby the circuit dynamically generates an pair of bitstreams, v 1 and v 2 , for output at the pair of outputs ports and the generating is performed using a symmetric line coding machine.
10. The apparatus of claim 9 where the symmetric line coding machine is a regular bitstream symmetric line coding machine.
11. The apparatus of claim 9 where the symmetric line coding machine is a complementary regular bitstream symmetric line coding machine.
12. The apparatus of claim 9 where the symmetric line coding machine is a binary complementary regular bitstream symmetric line coding machine.
13. The apparatus of claim 9 where the symmetric line coding machine includes a set of N parallel input lines and M parallel output lines.
14. The apparatus of claim 13 where the symmetric line coding machine includes a set of N parallel input lines and M parallel output lines is bitstream parallel-symmetric line coding machine.
15. The apparatus of claim 13 where the symmetric line coding machine includes a set of N parallel input lines and M parallel output lines is regular bitstream parallel-symmetric line coding machine.
16. The apparatus of claim 13 where the symmetric line coding machine machine includes a set of N parallel input lines and M parallel output lines is a complementary bitstream parallel-symmetric line coding machine.
17. The apparatus of claim 13 where the symmetric line coding machine machine includes a set of N parallel input lines and M parallel output lines is a binary complementary regular bitstream parallel-symmetric line coding machine.
18. The apparatus of claim 13 where the symmetric line coding machine machine includes a set of N parallel input lines and M parallel output lines and N=8 and M=8.