System and method for processing a high definition television (HDTV) image
View Patent ↗The present invention provides a system and method for processing a High Definition Television (HDTV) image. Specifically, the system and method of the present invention provides a plurality of programmable encoders connected in parallel and directly (i.e., gluelessly) attached to a HDTV video source. The system and method of the present invention allows a fall HDTV image to be received by each encoder at 74.25 MHz directly from the HDTV video source. Based on programming, each encoder will process only a portion of the full image.
1. A system for processing a High Definition Television (HDTV) image, comprising:
a plurality of video encoders connected in parallel;
wherein each of the encoders receives an entire image from a HDTV video source; and
wherein each of the encoders processes only a portion of the entire image.
2. The system of claim 1 , wherein the encoders are directly attached to the HDTV video source.
3. The system of claim 1 , wherein the encoders are MPEG-2 encoders.
4. The system of claim 1 , wherein each of the encoders comprises:
a digital video input interface for receiving the HDTV image directly from the HDTV video source; and
a programming system for programming each of the encoders to determine the portion of the entire image to be processed thereby.
5. The system of claim 4 , wherein the programming system comprises:
a quantity system for designating an encoder quantity;
a position system for designating a relative encoder position;
a processing system for designating a processing orientation;
an overlap system for designating an overlap between image portions; and
a size system for designating an image size.
6. The system of claim 4 , wherein the programming system comprises a plurality of programmable registers.
7. The system of claim 1 , wherein the encoders receive the image at a pixel clock rate of approximately 74.25 MHz.
8. The system of claim 1 , wherein each of the encoders receives a same entire image from the HDTV video source.
9. A system for processing a High Definition Television (HDTV) image, comprising:
a plurality of video encoders connected in parallel and directly attached to a HDTV video source; and
wherein each of the encoders receives an entire image from the HDTV video source, and wherein each of the encoders processes only a portion of the entire image.
10. The system of claim 9 , wherein each of the encoders comprises:
a digital video input interface for receiving the HDTV image directly from the HDTV video source; and
a programming system for programming each of the encoders to determine the portion of the entire image to be processed thereby.
11. The system of claim 10 , wherein the programming system comprises a plurality of programmable registers.
12. The system of claim 11 , wherein the plurality of programmable registers include:
a quantity register for designating an encoder quantity;
a position register for designating a relative encoder position;
a processing register for designating a processing orientation;
an overlap register for designating an overlap between image portions; and
a size register for designating an image size.
13. The system of claim 9 , wherein the encoders receive the image at a pixel clock rate of approximately 74.25 MHz.
14. The system of claim 9 , wherein each of the encoders receives a same entire image from the HDTV video source.
15. The system of claim 9 , wherein the encoders are MPEG-2 encoders.
16. A method for processing a High Definition Television (HDTV) image, comprising the steps of:
providing a plurality of video encoders connected in parallel and directly attached to a HDTV video source; and
programming each of the encoders to process only a portion of an entire image received from the HDTV video source wherein each of the encoders receives an entire image from the HDTV video source but processes only a portion thereof, based on the programming step.
17. The method of claim 16 , wherein the programming step comprises:
designating an encoder quantity;
designating an encoder position;
designating a processing orientation;
designating an overlap between image portions; and
designating an image size.
18. The method of claim 17 , wherein the step of designating an image size comprises designating an image size of up to approximately 1125 lines per video frame.
19. The method of claim 16 , wherein the receiving step comprises each of the encoders receiving the entire image from the HDTV video source at a pixel clock rate of approximately 74.25 MHz.