System analyzer for a data storage system
View Patent ↗A system analyzer for a data storage system has a control module and a memory module. The system analyzer includes a logic analyzer, an input port that couples to the data storage system, an output port that couples to the logic analyzer, and a pre-processor which is interconnected between the input port and the output port. The pre-processor is configured to receive, while a first point-to-point signal is exchanged between the control module and the memory module, a second point-to-point signal which is a copy of the first point-to-point signal. The pre-processor is further configured to generate a pre-processed signal based on the second point-to-point signal, and to provide the pre-processed signal to the logic analyzer.
1. A system analyzer for a data storage system having a control module and a memory module, the system analyzer comprising:
a logic analyzer;
an input port that couples to the data storage system;
an output port that couples to the logic analyzer;
a pre-processor which is interconnected between the input port and the output port, the pre-processor being configured to:
receive, while a first point-to-point signal is exchanged between the control module and the memory module, a second point-to-point signal which is a copy of the first point-to-point signal,
generate a pre-processed signal based on the second point-to-point signal, and
provide the pre-processed signal to the logic analyzer;
an adaptor module;
a cable having a first end which connects to the adaptor module, and a second end which connects to the input port, the adaptor module being configured to:
buffer the second point-to-point signal, and
pass the second point-to-point signal through the cable and the input port to the pre-processor;
another cable having a first end which connects to the output port and a second end which connects to the logic analyzer; the pre-processor, when providing the pre-processed signal to the logic analyzer, being configured to:
pass the preprocessed signal through the output port and the other cable to the logic analyzer.
2. The system analyzer of claim 1 wherein the pre-processor, when generating the pre-processor signal, is configured to:
determine whether the second point-to-point signal complies with a signaling protocol; and
create, as the pre-processed signal, a signal which includes (i) data from the second point-to-point signal and (ii) status indicating whether the second point-to-point signal complies with the signaling protocol.
3. The system analyzer of claim 1 wherein the second point-to-point signal includes information in an initially serialized form, and wherein the pre-processor, when generating the pre-processor signal, is configured to:
de-serialize the information of the second point-to-point signal; and
form, as the pre-processed signal, a signal which includes the de-serialized information of the second point-to-point signal.
4. The system analyzer of claim 1 wherein the pre-processor, when receiving the second point-to-point signal, is configured to:
obtain, while the first point-to-point signal travels through a backplane between the control module and the memory module, the second point-to-point signal from one of the control module and the memory module through the backplane.
5. The system analyzer of claim 1 wherein the adapter module is configured to (i) physically connect to a backplane which interconnects the control module and the memory module, and (ii) acquire the second point-to-point signal directly from the backplane.
6. An interface of a data storage system having a control module and a memory module, the interface comprising:
an input port that couples to the data storage system;
an output port that couples to a logic analyzer; and
a pre-processor which is interconnected between the input port and the output port, the pre-processor being configured to:
receive, while a first point-to-point signal is exchanged between the control module and the memory module, a second point-to-point signal which is a copy of the first point-to-point signal,
generate a pre-processed signal based on the second point-to-point signal,
provide the pre-processed signal to the logic analyzer;
an adaptor module;
a cable having a first end which connects to the adaptor module, and a second end which connects to the input port, the adaptor module being configured to:
buffer the second point-to-point signal, and
pass the second point-to-point signal through the cable and the input port to the pre-processor;
another cable having a first end which connects to the output port and a second end which connects to the logic analyzer; the pre-processor, when providing the pre-processed signal to the logic analyzer, being configured to:
pass the pre-processed signal through the output port and the other cable to the logic analyzer.
7. The interface of claim 6 wherein the pre-processor, when generating the pre-processor signal, is configured to:
determine whether the second point-to-point signal complies with a signaling protocol; and
create, as the pre-processed signal, a signal which includes (i) data from the second point-to-point signal and (ii) status indicating whether the second point-to-point signal complies with the signaling protocol.
8. The interface of claim 6 wherein the second point-to-point signal includes information in an initially serialized form, and wherein the pre-processor, when generating the pre-processor signal, is configured to:
de-serialize the information of the second point-to-point signal; and
form, as the pre-processed signal, a signal which includes the de-serialized information of the second point-to-point signal.
9. The interface of claim 6 wherein the pre-processor, when receiving the second point-to-point signal, is configured to:
obtain, while the first point-to-point signal travels through a backplane between the control module and the memory module, the second point-to-point signal from one of the control module and the memory module through the backplane.
10. The interface of claim 6 wherein the adapter module is configured to (i) physically connect to a backplane which interconnects the control module and the memory module, and (ii) acquire the second point-to-point signal directly from the backplane.
11. A method for monitoring operation of a data storage system having a control module and a memory module, the method comprising the steps of:
simultaneously generating a first point-to-point signal and a second point-to-point signal on separate outputs of an integrated circuit so that (i) the first point-to-point signal travels through a first point-to-point channel between the control module and the memory module, and (ii) the second point-to-point signal travels through a second point-to-point channel between an adaptor module and one of the control module and the memory module;
while the first point-to-point signal is exchanged between the control module and the memory module, receiving the second point-to-point signal which is a copy of the first point-to-point signal;
buffering the second point-to-point signal after the step of receiving the second point-to-point signal;
passing the second point-to-point signal through a cable to a pre-processor;
after the step of passing, generating a pre-processed signal based on the second point-to-point signal; and
providing the pre-processed signal to a logic analyzer, the step of providing the pre-processed signal to the logic analyzer including the step of passing the pre-processed signal through another cable to the logic analyzer.
12. The method of claim 11 wherein the step of generating the pre-processor signal includes the steps of:
determining whether the second point-to-point signal complies with a signaling protocol; and
creating, as the pre-processed signal, a signal which includes (i) data from the second point-to-point signal and (ii) status indicating whether the second point-to-point signal complies with the signaling protocol.
13. The method of claim 11 wherein the second point-to-point signal includes information in an initially serialized form, and wherein the step of generating the pre-processor signal includes the steps of:
de-serializing the information of the second point-to-point signal; and
forming, as the pre-processed signal, a signal which includes the de-serialized information of the second point-to-point signal.
14. The method of claim 11 wherein the step of receiving the second point-to-point signal includes the step of:
while the first point-to-point signal travels through a backplane between the control module and the memory module, obtaining the second point-to-point signal from one of the control module and the memory module through the backplane.
15. The method of claim 11 , further comprising the step of:
physically connecting an adapter module to a backplane which interconnects the control module and the memory module, and wherein the step of receiving the second point-to-point signal includes the step of the adapter module acquiring the second point-to-point signal directly from the backplane.
16. A method for monitoring operation of a data storage system having a control module and a memory module, the method comprising the steps of:
sensing a first point-to-point signal from a first circuit board trace leading from a first circuit board component;
generating, from an amplifier circuit that is different than the first circuit board component, a second point-to-point signal on a second circuit board trace that is electrically isolated from the first circuit board trace so that (i) the first point-to-point signal travels through a first point-to-point channel between the control module and the memory module, and (ii) the second point-to-point signal travels through a second point-to-point channel between an adaptor module and one of the control module and the memory module;
while the first point-to-point signal is exchanged between the control module and the memory module, receiving the second point-to-point signal which is a copy of the first point-to-point signal;
buffering the second point-to-point signal after the step of receiving the second point-to-point signal;
passing the second point-to-point signal through a cable to a pre-processor;
after the step of passing, generating a pre-processed signal based on the second point-to-point signal; and
providing the pre-processed signal to a logic analyzer, the step of providing the pre-processed signal to the logic analyzer including the step of passing the pre-processed signal through another cable to the logic analyzer.
17. The method of claim 16 , further comprising the step of:
physically connecting an adapter module to a backplane which interconnects the control module and the memory module, and wherein the step of receiving the second point-to-point signal includes the step of the adapter module acquiring the second point-to-point signal directly from the backplane.
18. A system analyzer for a data storage system having multiple control modules and multiple memory modules, the system analyzer comprising:
a logic analyzer;
multiple pre-processors which are interconnected between the data storage system and the logic analyzer, each pre-processor being configured to:
receive a point-to-point signal which is a copy of another point-to-point signal,
generate a pre-processed signal based on that received point-to-point signal, and
provide that generated pre-processed signal to the logic analyzer; and
multiple expansion chassis interconnected between the multiple pre-processors and the logic analyzer, each expansion chassis being configured to:
receive pre-processed signals from a corresponding one of the pre-processors, and
direct the received pre-processed signals to the logic analyzer.
19. The system analyzer of claim 18 wherein each pre-processor is configured to provide pre-processed signals to a corresponding expansion chassis in a multiplexed manner.
20. The system analyzer of claim 18 wherein the data storage system further has a backplane that interconnects the multiple control modules and the multiple memory modules, and wherein the system analyzer further comprises:
an adapter module which is configured to (i) physically connect to the backplane, (ii) acquire point-to-point signals directly from the backplane, and (iii) convey the point-to-point signals to the multiple pre-processors.