40/80-core cable discriminating method and system performing exact discrimination although master and slave storage apparatuses are connected host

1. A 40/80-core cable discriminating method of discriminating between an 80-core cable having eighty core-wires and a 40-core cable having forty core-wires, the 40-core or the 80-core cable being connected between a host and a peripheral storage apparatus so as to form an IDE (Integrated Drive Electronics) bus defined by an ATA (AT Attachment) abbreviated to an ATA (IDE) bus, the 80-core cable being capable of performing transmission at a data transmitting speed not less than 66 MB/S supported on an ultra DMA (ultra Direct Memory Access) system related to the ATA (IDE) bus, the host being capable of detecting a PDIAG-signal which is used for the ATA (IDE) bus and which is generated by the peripheral storage apparatus, said method comprising:

setting a detecting period for detecting a first state of the PDIAG-signal, said detecting period being not shorter than a first time needed to change the PDIAG-signal into said first state; and

discriminating, by detecting the state of the PDIAG-signal during said detecting period, which of the 40-core cable and the 80-core cable is used,

wherein the 40-core cable is discriminated as being used if the state of the PDIAG-signal comprises a first predetermined state and the 80-core cable is discriminated as being used if the state of the PDIAG-signal comprises a second predetermined state,

wherein, when master and slave storage apparatuses as the peripheral storage apparatus are connected to the host, a protocol period is adopted as said detecting period,

wherein said protocol period comprises the sum of a first protocol period, a second protocol period and a third protocol period,

wherein said first protocol period comprises a period that an SRST signal is provided to the peripheral storage apparatus, said SRST signal serving to command the peripheral storage apparatus to perform a software-resetting,

wherein said second protocol period comprises a period that the peripheral storage apparatus changes the PDIAG-signal into said first state within the PDIAG-signal has been settled into said first state, and

wherein said third protocol period comprises a period that the PDIAG-signal is kept on said first state while the SRST signal is in said first state.

2. A 40/80-core cable discriminating method as claimed in claim 1 , further comprising:

providing the peripheral storage apparatus with an SRST signal for commanding the peripheral storage apparatus to perform a software-resetting, the PDIAG-signal being changed into said first state when the peripheral storage apparatus is provided with said SRST signal; and

setting a second time needed to change the SRST signal into said first state, said discriminating comprising discriminating which of the 40-core cable and or the 80-core cable is used after said second time has passed.

3. A 40/80-core cable discriminating method as claimed in claim 2 , wherein said second time is not shorter than 5 μS.

4. A 40/80-core discriminating method as claimed in claim 2 , wherein said PDIAG-signal is changed into said high state when the peripheral storage apparatus is provided with said SRST signal.

5. A 40/80-core discriminating method as claimed in claim 2 , further comprising:

releasing said SRST signal after said discriminating so that said SRST signal is changed to said low state.

6. A 40/80-core cable discriminating method as claimed in claim 1 , wherein said first time is not shorter than 1 mS.

7. A 40/80-core cable discriminating method as claimed in claim 1 , wherein said first time is not shorter than 1 mS.

8. A 40/80-core cable discriminating method as claimed in claim 1 , wherein, when only a master storage apparatus as the peripheral storage apparatus is connected to the host, said discriminating comprises discriminating that the 40-core cable is used if the PDIAG-signal takes the first state while that the 80-core cable is used if the PDIAG-signal takes a second state.

9. A 40/80-core cable discriminating method as claimed in claim 1 , wherein the 40-core cable is discriminated as being used if the state of the PDIAG-signal comprises a high state arid the 80-core cable is discriminated as being used if the state of the PDIAG-signal comprises a low state.

10. A 40/80-core cable discriminating system for discriminating between an 80-core cable having eighty core-wires and a 40-core cable having forty core-wires, the 40-core or the 80-core cable being connected between a host and a peripheral storage apparatus so as to form an IDE (Integrated Drive Electronics) bus defined by an ATA (AT Attachment) abbreviated to an ATA (IDE) bus, the 80-core cable being capable of performing transmission at a data transmitting speed not less than 66 MB/S supported on an ultra DMA (ultra Direct Memory Access) system related to the ATA (IDE) bus, the host being capable of detecting a PDIAG-signal which is used for the ATA (IDE) bus and which is generated by the peripheral storage apparatus, said system comprising:

a detecting period setting unit for setting a detecting period for detecting a first state of the PDIAG-signal, said detecting period being not shorter than a first time needed to change the PDIAG-signal into said first state; and

a 40/80-core cable discriminating unit for discriminating, by detecting the state of the PDIAG-signal during said detecting period, which of the 40-core cable and the 80-core cable is used,

wherein the 40-core cable is discriminated as being used if the state of the PDIAG-signal comprises a first predetermined state and the 80-core cable is discriminated as being used if the state of the PDIAG-signal comprises a second predetermined state,

wherein, when master and slave storage apparatuses as the peripheral storage apparatus are connected to the host, a protocol period is adapted as said detecting period,

wherein said protocol period comprises the sum of a first protocol period, a second protocol period and a third protocol period,

wherein said first protocol period comprises a period that an SRST (software reset) signal is provided to the peripheral storage apparatus, said SRST signal serving to command the peripheral storage apparatus to perform a software-resetting,

wherein said second protocol period comprises a period that the peripheral storage apparatus changes the PDIAG-signal into said first state within the PDIAG-signal has been settled into said first state, and

wherein said third protocol period comprises a period that the PDIAG-signal is kept on said first state while the SRST signal is in said first state.

11. A 40/80-core cable discriminating system as claimed in claim 10 , wherein said system further comprises:

an SRST (software reset) signal providing unit for providing the peripheral storage apparatus with an SRST signal for commanding the peripheral storage apparatus to perform a software-resetting, the PDIAG-signal being changed into said first state when the peripheral storage apparatus is provided with said SRST signal; and

a second time setting unit for setting a second time needed to change the SRST signal into said first state, said 40/80-core cable discriminating unit being for discriminating which of the 40-core cable and the 80-core cable is used after said second time has passed.

12. A 40/80-core cable discriminating system as claimed in claim 11 , wherein said second time is not shorter than 5 μS.

13. A 40/80-core cable discriminating system as claimed in claim 11 , further comprising:

a PDIAG-signal driver for changing the state of the PDIAG-signal.

14. A 40/80-core cable discriminating system as claimed in claim 10 , wherein said first time is not shorter than 1 mS.

15. A 40/80-core cable discriminating system as claimed in claim 10 , wherein said second time is not shorter than 1 mS.

16. A 40/80-core cable discriminating system as claimed in claim 10 , wherein, when only a master storage apparatus as the peripheral storage apparatus is connected to the host, said 40/80-core cable discriminating unit comprises a unit for discriminating that the 40-core cable is used if the PDIAG-signal takes the first state and that the 80-core cable is used if the PDIAG-signal takes a second state.

17. A 40/80-core cable discriminating system as claimed in claim 10 , wherein the 40-core cable is discriminated as being used if the state of the PDIAG-signal comprises a high state and the 80-core cable is discriminated as being used if the state of the PDlAG-signal comprises a low state.

18. A 40/80-core cable discriminating method of discriminating between an 80-core cable having eighty core-wires and a 40-core cable having forty core-wires, the 40-core or the 80-core cable being connected between a host and a peripheral storage apparatus so as to form an IDE (Integrated Drive Electronics) bus defined by an ATA (AT Attachment) abbreviated to an ATA (IDE) bus, the 80-core cable being capable of performing transmission at a data transmitting speed not less than 66 MB/S supported on an ultra DMA (ultra Direct Memory Access) system related to the ATA (IDE) bus, the host being capable of detecting a PDIAG-signal which is used for the ATA (IDE) bus and which is generated by the peripheral storage apparatus, said method comprising:

setting a detecting period for detecting a first state of the PDIAG-signal, said detecting period being not shorter than a first time needed to change the PDIAG-signal into said first state; and

discriminating, by detecting the state of the PDIAG-signal during said detecting period, which of the 40-core cable and the 80-core cable is used,

wherein the 40-core cable is discriminated as being used if the state of the PDIAG-signal comprises a first predetermined state and the 80-core cable is discriminated as being used if the state of the PDIAG-signal comprises a second predetermined state,

wherein, when master and slave apparatuses as the peripheral storage apparatus are connected to the host, a protocol period is adopted as said detecting period,

wherein said protocol period comprises the sum of a first protocol period, a second protocol period and a third protocol period, and

wherein said first protocol period comprises a period that an SRST signal is provided to the peripheral storage apparatus, said SRST signal serving to command the peripheral storage apparatus to perform a software-resetting.

19. A 40/80-core cable discriminating method of discriminating between an 80-core cable having eighty core-wires and a 40-core cable having forty core-wires, the 40-core or the 80-core cable being connected between a host and a peripheral storage apparatus so as to form an IDE (Integrated Drive Electronics) bus defined by an ATA (AT Attachment) abbreviated to an ATA (IDE) bus, the 80-core cable being capable of performing transmission at a data transmitting speed not less than 66 MB/S supported on an ultra DMA (ultra Direct Memory Access) system related to the ATA (IDE) bus, the host being capable of detecting a PDIAG-signal which is used for the ATA (IDE) bus and which is generated by the peripheral storage apparatus, said method comprising:

setting a detecting period for detecting a first state of the PDIAG-signal, said detecting period being not shorter than a first time needed to change the PDIAG-signal into said first state; and

discriminating, by detecting the state of the PDIAG-signal during said detecting period, which of the 40-core cable and the 80-core cable is used,

wherein the 40-core cable is discriminated as being used if the state of the PDIAG-signal comprises a first predetermined state and the 80-core cable is discriminated as being used, if the state of the PDIAG-signal comprises a second predetermined state,

wherein, when master and slave apparatuses as the peripheral storage apparatus are connected to the host, a protocol period is adopted as said detecting period,

wherein said protocol period comprises the sum of a first protocol period, a second protocol period and a third protocol period, and

wherein said second protocol period comprises a period that an SRST signal is provided to the peripheral storage apparatus, said SRST signal serving to command the peripheral storage apparatus to perform a software-resetting.

20. A 40/80-core cable discriminating method of discriminating between an 80-core cable having eighty core-wires and a 40-core cable having forty core-wires, the 40-core or the 80-core cable being connected between a host and a peripheral storage apparatus so as to form an IDE (Integrated Drive Electronics) bus defined by an ATA (AT Attachment) abbreviated to an ATA (IDE) bus, the 80-core cable being capable of performing transmission at a data transmitting speed not less than 66 MB/S supported on an ultra DMA (ultra Direct Memory Access) system related to the ATA (IDE) bus, the host being capable of detecting a PDIAG-signal which is used for the ATA (IDE) bus and which is generated by the peripheral storage apparatus, said method comprising:

setting a detecting period for detecting a first state of the PDIAG-signal, said detecting period being not shorter than a first time needed to change the PDIAG-signal into said first state; and

discriminating, by detecting the state of the PDIAG-signal during said detecting period, which of the 40-core cable and the 80-core cable is used,

wherein the 40-core cable is discriminated as being used if the state of the PDIAG-signal comprises a first predetermined state and the 80-core cable is discriminated as being used if the state of the PDIAG-signal comprises a second predetermined state,

wherein, when master and slave apparatuses as the peripheral storage apparatus are connected to the host, a protocol period is adopted as said detecting period,

wherein said protocol period comprises the sum of a first protocol period, a second protocol period and a third protocol period, and

wherein said third protocol period comprises a period that the peripheral storage apparatus changes the PDIAG-signal into said first state within the PDIAG-signal has been settled into said first state.

21. A 40/80-core cable discriminating system for discriminating between an 80-core cable having eighty core-wires and a 40-core cable having forty core-wires, the 40-core or the 80-core cable being connected between a host and a peripheral storage apparatus so as to form an IDE (Integrated Drive Electronics) bus defined by an ATA (AT Attachment) abbreviated to an ATA (IDE) bus, the 80-core cable in capable of performing transmission at a data transmitting speed not less than 66 MB/S supported on an ultra DMA (ultra Direct Memory Access) system related to the ATA (IDE) bus, the host being capable of detecting a PDIAG-signal which is used for the ATA (IDE) bus and which is generated by the peripheral storage apparatus, said system comprising:

means for setting a detecting period for detecting a first state of the PDIAG-signal, said detecting period being not shorter than a first time needed to change the PDIAG-signal into said first state; and

means for discriminating, by detecting the state of the PDIAG-signal during said detecting period, which of the 40-core cable and the 80-core cable is used,

wherein the 40-core cable is discriminated as being used if the state of the PDIAG-signal comprises a first predetermined state and the 80-core cable is discriminated as being used if the state of the PDIAG-signal comprises a second predetermined state,

wherein, when master and slave apparatuses as the peripheral storage apparatus are connected to the host, a protocol period is adopted as said detecting period,

wherein said protocol period comprises the sum of a first protocol period, a second protocol period and a third protocol period, and

wherein said first protocol period comprises a period that an SRST signal is provided to the peripheral storage apparatus, said SRST signal serving to command the peripheral storage apparatus to perform a software-resetting.

22. A 40/80-core cable discriminating system as claimed in claim 21 ,

means for providing the peripheral storage apparatus with an SRST signal for commanding the peripheral storage apparatus to perform a software-resetting, the PDIAG-signal being changed into said first state when the peripheral storage apparatus is provided with said SRST signal; and

means for setting a second time needed to change the SRST signal into said first state, said discriminating comprising discriminating which of the 40-core cable and the 80-core cable is used after said second time has passed.

23. A 40/80-core cable discriminating method as claimed in claim 21 , wherein the 40-core cable is discriminated as being used if the state of the PDIAG-signal comprises a high state and the 80-core cable is discriminated as being used if the state of the PDIAG-signal comprises a low state.

24. A 40/80-core cable discriminating system for discriminating between an 80-core cable having eighty core-wires and a 40-core cable having forty core-wires, the 40-core or the 80-core cable being connected between a host and a peripheral storage apparatus so as to form an IDE (Integrated Drive Electronics) bus defined by an ATA (AT Attachment) abbreviated to an ATA (IDE) bus, the 80-core cable being capable of performing transmission at a data transmitting speed not less than 66 MB/S supported on an ultra DMA (ultra Direct Memory Access) system related to the ATA (IDE) bus, the host being capable of detecting a PDIAG-signal which is used for the ATA (IDE) bus and which is generated by the peripheral storage apparatus, said system comprising:

means for setting a detecting period for detecting a first state of the PDIAG-signal, said detecting period being not shorter than a first time needed to change the PDIAG-signal into said first state; and

means for discriminating, by detecting the state of the PDIAG-signal during said detecting period, which of the 40-core cable and the 80-core cable is used,

wherein the 40-core cable is discriminated as being used if the state of the PDIAG-signal comprises a first predetermined state and the 80-core cable is discriminated as being used if the state of the PDIAG-signal comprises a second predetermined state,

wherein, when master and slave apparatuses as the peripheral storage apparatus are connected to the host, a protocol period is adopted as said detecting period,

wherein said protocol period comprises the sum of a first protocol period, a second protocol period and a third protocol period, and

wherein said second protocol period comprises a period that an SRST signal is provided to the peripheral storage apparatus, said SRST signal serving to command the peripheral storage apparatus to perform a software-resetting.

25. A 40/80-core cable discriminating system for discriminating between an 80-core cable having eighty core-wires and a 40-core cable having forty core-wires, the 40-core or the 80-core cable being connected between a host and a peripheral storage apparatus so as to form an IDE (Integrated Drive electronics) bus defined by an ATA (AT Attachment) abbreviated to an ATA (IDE) bus, the 80-core cable being capable of performing transmission at a data transmitting speed not less than 66 MB/S supported on an ultra DMA (ultra Direct Memory Access) system related to the ATA (IDE) bus, the host being capable of detecting a PDIAG-signal which is used for the ATA (IDE) bus and which is generated by the peripheral storage apparatus, said system comprising:

means for setting a detecting period for detecting a first state of the PDIAG-signal, said detecting period being not shorter than a first time needed to change the PDIAG-signal into said first state; and

means for discriminating, by detecting the state of the PDIAG-signal during said detecting period, which of the 40-core cable and the 80-core cable is used,

wherein the 40-core cable is discriminated as being used if the state of the PDIAG-signal comprises a first predetermined state and the 80-core cable is discriminated as being used if the state of the PDIAG-signal a second predetermined state,

wherein, when master and slave apparatuses as the peripheral storage apparatus are connected to the host, a protocol period is adopted as said detecting period,

wherein said protocol period comprises the sum of a first protocol period, a second protocol period and a third protocol period, and

wherein said third protocol period comprises a period that the peripheral storage apparatus changes the PDIAG-signal into said first state within the PDIAG-signal has been settled into said first state.