IP Library Granted Patent US 7,075,951
Granted Patent B1
US 7,075,951 · App. 10/102,461 · Granted Jul 11, 2006

Method and apparatus for the operation of a storage unit in a network element

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Quick Facts
Patent No.
US 7,075,951
App. No.
10/102,461
Granted
Jul 11, 2006
Kind
B1
Abstract

In an embodiment, an apparatus includes a storage unit to store data from a data signal. The apparatus also includes control circuitry coupled to the storage unit. The control circuitry is to cause the storage of the data from the data signal into the storage unit at a nominal rate upon determining that the data signal includes a number of errors.

Claims (50)

1. A method comprising:

receiving a data signal;

determining the data signal includes a number of errors; and

processing the data signal as if the data signal is independent of the number of errors and is operating at a nominal rate for the data signal, wherein the processing is to include transmitting the data within the data signal into a first-in-first-out (FIFO) memory unit.

2. The method of claim 1 , wherein the processing is to include substituting current stuffing data of the data signal with stuffing data for a data signal operating at the nominal rate.

3. The method of claim 2 , wherein the stuffing data for the data signal operating at the nominal rate includes a predetermined pattern of variable stuffing bits.

4. The method of claim 1 , wherein the FIFO memory unit is within a network element and wherein determining the data signal includes the number of errors comprises receiving an indication from a different network element that the data signal includes the number of errors, wherein the different network element is coupled to the network element and is transmitting the data signal to the network element.

5. The method of claim 1 , wherein the nominal rate for the data signal comprises a nominal rate for a Synchronous Optical Network signal.

6. A method comprising:

receiving a data signal;

determining the data signal includes a number of errors; and

generating a different data signal, the different data signal operating at a nominal rate for the data signal; and

transmitting data within the different data signal into a first-in-first-out (FIFO) memory unit.

7. The method of claim 6 , wherein the different data signal comprises stuffing data.

8. The method of claim 7 , wherein the stuffing data for the different data signal operating at the nominal rate includes a predetermined pattern of variable stuffing bits.

9. The method of claim 6 , wherein the FIFO memory unit is within a network element and wherein determining the data signal includes the number of errors comprises receiving an indication from a different network element that the data signal includes the number of errors, wherein the different network element is coupled to the network element and is transmitting the data signal to the network element.

10. The method of claim 6 , wherein the nominal rate for the data signal comprises a nominal rate for a Synchronous Optical Network signal.

11. An apparatus comprising:

a storage unit to store data from a data signal; and

control circuitry coupled to the storage unit, the control circuitry to cause the storage of the data from the data signal into the storage unit at a nominal rate upon determining that the data signal includes a number of errors.

12. The apparatus of claim 11 , wherein causing, by the control circuitry, the inputting of the data from the data signal into the storage unit at the nominal rate upon determining that the data signal includes a number of errors comprises substituting current stuffing data of the data signal with stuffing data for a data signal operating at the nominal rate.

13. The apparatus of claim 11 , comprising a frequency phase detector unit coupled to the storage unit and the control circuitry, the frequency phase detector unit to receive a depth value of the storage unit from the storage unit, wherein the frequency phase detector unit is to generate a signal corresponding to the depth value.

14. The apparatus of claim 13 , comprising a low-pass filter unit coupled to the frequency phase detector unit, the low-pass filter unit to receive the signal corresponding to the depth value and wherein the low-pass filter unit is to generate a filtered signal based on the signal corresponding to the depth value.

15. The apparatus of claim 14 , comprising a voltage-controlled crystal oscillator unit coupled to the low-pass filter unit and the storage unit, the voltage-controlled crystal oscillator unit to receive the filtered signal and to generate a clock signal, wherein the voltage-controlled crystal oscillator unit is to transmit the clock signal to the storage unit, the clock signal to control an output rate of the storage unit.

16. The apparatus of claim 11 , wherein the storage unit comprises a first-in-first-out unit.

17. The apparatus of claim 11 , wherein the nominal rate for the data signal comprises a nominal rate for a Synchronous Optical Network signal.

18. A line card in a network element comprising:

a first-in-first-out (FIFO) unit to store Data Signal (DS) data from a Synchronous Optical Network (SONET) signal; and

control circuitry coupled to the FIFO unit, the control circuitry to cause inputting of data into the FIFO unit at a rate for the SONET signal upon determining that the SONET signal is invalid.

19. The line card of claim 18 , comprising a frequency phase detector unit coupled to the FIFO unit and the control circuitry, the frequency phase detector unit to receive a depth value of the FIFO unit from the FIFO unit, wherein the frequency phase detector unit is to generate a signal corresponding to the depth value.

20. The line card of claim 19 , comprising a low-pass filter unit coupled to the frequency phase detector unit, the low-pass filter unit to receive the signal corresponding to the depth value and wherein the low-pass filter unit is to generate a filtered signal based on the signal corresponding to the depth value.

21. The line card of claim 20 , comprising a voltage-controlled crystal oscillator unit coupled to the low-pass filter unit and the FIFO unit, the voltage-controlled crystal oscillator unit to receive the filtered signal and to generate a clock signal, wherein the voltage-controlled crystal oscillator unit is to transmit the clock signal to the FIFO unit, the clock signal to control an output rate of the FIFO unit.

22. The line card of claim 18 , wherein causing, by the control circuitry, the inputting of the data from the data signal into the FIFO unit at the rate for the SONET signal upon determining that the SONET signal is invalid comprises substituting current stuffing data of the SONET signal with stuffing data for a data signal operating at the rate for a SONET signal.

23. A system comprising:

a number of line cards comprising,

a first-in-first-out (FIFO) unit to store data from a data signal; and

control circuitry coupled to the FIFO unit, the control circuitry to cause inputting of data into the FIFO unit at a nominal rate for the data signal upon determining that the data signal is invalid; and

a number of control cards coupled to the number of line cards, the number of control cards to transmit provisioning data associated with the data signal to the number of line cards.

24. The system of claim 23 , comprising a frequency phase detector unit coupled to the FIFO unit and the control circuitry, the frequency phase detector unit to receive a depth value of the FIFO unit from the FIFO unit, wherein the frequency phase detector unit is to generate a signal corresponding to the depth value.

25. The system of claim 24 , comprising a low-pass filter unit coupled to the frequency phase detector unit, the low-pass filter unit to receive the signal corresponding to the depth value and wherein the low-pass filter unit is to generate a filtered signal based on the signal corresponding to the depth value.

26. The system of claim 25 comprising a voltage-controlled crystal oscillator unit coupled to the low-pass filter unit and the FIFO unit, the voltage-controlled crystal oscillator unit to receive the filtered signal and to generate a clock signal, wherein the voltage-controlled crystal oscillator unit is to transmit the clock signal to the FIFO unit, the clock signal to control an output rate of the FIFO unit.

27. The system of claim 23 , wherein causing, by the control circuitry, the inputting of the data from the data signal into the FIFO unit at a nominal rate for the data signal upon determining that the data signal is invalid comprises substituting current stuffing data of the data signal with stuffing data for a data signal operating at the nominal rate for a data signal.

28. A machine-readable medium that provides instructions, which when executed by a machine, causes the machine to perform operations comprising:

receiving a data signal;

determining the data signal includes a number of errors; and

processing the data signal as if the data signal is independent of the number of errors and is operating at a nominal rate for the data signal, wherein the processing is to include transmitting the data within the data signal into a first-in-first-out (FIFO) memory unit.

29. The machine-readable medium of claim 28 , wherein the processing is to include substituting current stuffing data of the data signal with stuffing data for a data signal operating at the nominal rate.

30. The machine-readable medium of claim 29 , wherein the stuffing data for the data signal operating at the nominal rate includes a predetermined pattern of variable stuffing bits.

31. The machine-readable medium of claim 28 , wherein the FIFO memory unit is within a network element and wherein determining the data signal includes the number of errors comprises receiving an indication from a different network element that the data signal includes the number of errors, wherein the different network element is coupled to the network element and is transmitting the data signal to the network element.

32. The machine-readable medium of claim 28 , wherein the nominal rate for the data signal comprises a nominal rate for a Synchronous Optical Network signal.

Assignments (3)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Feb 26, 2010
From: REDBACK NETWORKS INC.
To: ERICSSON AB
Reel/Frame 024002/0363 →
RELEASE Recorded Jan 11, 2007
From: SILICON VALLEY BANK
To: REDBACK NETWORKS, INC.
Reel/Frame 018855/0108 →
SECURITY AGREEMENT Recorded Apr 7, 2004
From: REDBACK NETWORKS INC.
To: SILICON VALLEY BANK
Reel/Frame 014499/0957 →