Frequency-modulated signal receiver with digital demodulator
View Patent ↗A receiver of a frequency-modulated signal is provided. The receiver includes a frequency-transposition unit for lowering the frequency of the frequency-modulated signal, and a digital demodulator for regenerating a digital signal from the frequency-transposed signal. The frequency-transposition unit includes a local oscillator for generating a local oscillator signal used in lowering the frequency of the frequency-modulated signal. The frequency-transposed signal is sampled in the digital demodulator at the rate of a sampling signal, and the sampling signal is generated by the local oscillator of the frequency-transposition unit. In a preferred embodiment, the local oscillator includes at least one frequency-divider circuit that delivers the sampling signal. Also provided is a method for regenerating a digital signal from a frequency-modulated signal.
1. A receiver of a frequency-modulated signal representing a digital signal, the receiver comprising:
a frequency-transposition unit for lowering the frequency of the frequency-modulated signal so as to produce a frequency-transposed signal; and
a digital demodulator for regenerating the digital signal from the frequency-transposed signal, the frequency-transposed signal being sampled in the digital demodulator at the rate of a sampling signal,
wherein the frequency-transposition unit includes a phase-locked loop for generating a first signal used in lowering the frequency of the frequency-modulated signal, and
the sampling signal is generated by the phase-locked loop of the frequency-transposition unit.
2. The receiver according to claim 1 ,
wherein the frequency-transposition unit further comprises a reference oscillator that is coupled to the phase-locked loop, and
the phase-locked loop has a feedback portion that includes first and second cascade-connected frequency-divider circuits.
3. The receiver according to claim 2 , wherein the sampling signal is delivered by the first frequency-divider circuit.
4. The receiver according to claim 1 , wherein the phase-locked loop includes at least one frequency-divider circuit.
5. The receiver according to claim 4 , wherein the sampling signal is delivered by the frequency-divider circuit.
6. An integrated circuit including a receiver of a frequency-modulated signal representing a digital signal, the receiver comprising:
a frequency-transposition unit for lowering the frequency of the frequency-modulated signal so as to produce a frequency-transposed signal; and
a digital demodulator for regenerating the digital signal from the frequency-transposed signal, the frequency-transposed signal being sampled in the digital demodulator at the rate of a sampling signal,
wherein the frequency-transposition unit includes a phase-locked loop for generating a first signal used in lowering the frequency of the frequency-modulated signal, and
the sampling signal is generated by the phase-locked loop of the frequency-transposition unit.
7. The integrated circuit according to claim 6 ,
wherein the frequency-transposition unit further comprises a reference oscillator that is coupled to the phase-locked loop, and
the phase-locked loop has a feedback portion that includes first and second cascade-connected frequency-divider circuits.
8. The integrated circuit according to claim 7 , wherein the sampling signal is delivered by the first frequency-divider circuit.
9. The integrated circuit according to claim 6 , wherein the phase-locked loop includes at least one frequency-divider circuit that delivers the sampling signal.
10. An information processing system including at least one receiver of a frequency-modulated signal that represents a digital signal, the receiver comprising:
a frequency-transposition unit for lowering the frequency of the frequency-modulated signal so as to produce a frequency-transposed signal; and
a digital demodulator for regenerating the digital signal from the frequency-transposed signal, the frequency-transposed signal being sampled in the digital demodulator at the rate of a sampling signal,
wherein the frequency-transposition unit includes a phase-locked loop for generating a first signal used in lowering the frequency of the frequency-modulated signal, and
the sampling signal is generated by the phase-locked loop of the frequency-transposition unit.
11. The information processing system according to claim 10 ,
wherein the frequency-transposition unit further comprises a reference oscillator that is coupled to the phase-locked loop, and
the phase-locked loop has a feedback portion that includes first and second cascade-connected frequency-divider circuits.
12. The information processing system according to claim 11 , wherein the sampling signal is delivered by the first frequency-divider circuit.
13. The information processing system according to claim 10 , wherein the phase-locked loop includes at least one frequency-divider circuit that delivers the sampling signal.
14. A method for regenerating a digital signal from a frequency-modulated signal that represents the digital signal, said method comprising the steps of:
using a phase-locked loop of a frequency-transposition unit to generate a first signal;
using the first signal generated by the phase-locked loop of the frequency-transposition unit to lower the frequency of the frequency-modulated signal so as to produce a frequency-transposed signal;
using the phase-locked loop of the frequency-transposition unit to generate a sampling signal from the first signal generated by the phase-locked loop of the frequency-transposition unit;
sampling the frequency-transposed signal at the rate of the sampling signal; and
regenerating the digital signal from the frequency-transposed signal.
15. The method according to claim 14 , wherein the step of using the phase-locked loop of the frequency-transposition unit to generate the sampling signal includes the sub-step of using a frequency divider of the phase-locked loop for frequency-dividing the first signal to produce the sampling signal.
16. The method according to claim 14 , wherein the step of using the phase-locked loop of the frequency-transposition unit to generate the first signal comprises:
generating a reference signal; and
using the phase-locked loop to produce the first signal from the reference signal.
17. The method according to claim 16 , wherein the step of using the phase-locked loop of the frequency-transposition unit to generate the sampling signal includes the sub-step of using a frequency divider of the phase-locked loop for frequency-dividing the first signal to produce the sampling signal.
18. The receiver according to claim 1 ,
wherein the phase-locked loop includes a voltage-controlled oscillator, a first frequency-divider circuit having an input coupled to an output of the voltage-controlled oscillator, and a second frequency-divider circuit having an input coupled to the output of the first frequency-divider circuit, and
the sampling signal is provided by the output of the first frequency-divider circuit.
19. The receiver according to claim 18 , wherein the first signal is provided by the output of the voltage-controlled oscillator.
20. The receiver according to claim 1 ,
wherein the frequency-transposition unit further comprises a reference oscillator having an output that is connected to an input of the phase-locked loop, and
the output of the reference oscillator does not provide the sampling signal.