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App. No. 10/103,887 · Confirmation No. 4302

Layout method for semiconductor integrated circuit

Inventor: Tomoko Ide
Abandoned -- Failure to Respond to an Office Action View Publication ↗
⬇ PDF
 Code Description Pages PDF
2002-03-25 TRNA Transmittal of New Application 1 View
2002-03-25 SPEC Specification 16 View
2002-03-25 CLM Claims 3 View
2002-03-25 ABST Abstract 1 View
2002-03-25 DRW Drawings-only black and white line drawings 6 View
2002-03-25 OATH Oath or Declaration filed 2 View
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Quick Facts
App. No.
10/103,887
Filed
2002-03-25
Pub. No.
US20020141257A1
Examiner
TAT, BINH C
Art Unit
2825