Methods and apparatus for speculative probing with early completion and early request

1. A computer system, comprising:

a first cluster including a first plurality of processors and a first cache coherence controller, the first plurality of processors and the first cache coherence controller interconnected in a point-to-point architecture;

a second cluster including a second plurality of processors and a second cache coherence controller, the second plurality of processors and the second cache coherence controller interconnected in a point-to-point architecture, the first cache coherence controller coupled to the second cache coherence controller;

wherein the first cache coherence controller is configured to receive a cache access request originating from the first plurality of processors and send a probe to the first plurality of processors in the first cluster before the cache access request is received by a serialization point in the second cluster and wherein the first cache coherence controller is further configured to forward the cache access request before determining if the cache access request can be completed locally.

2. The computer system of claim 1 , wherein the cache access request can be completed locally if the cache access request is a read and the state of the cache corresponding to the cache access request is valid.

3. The computer system of claim 2 , wherein the cache access request can be completed locally if the cache access request is a write and the state of the cache corresponding to the cache access request is valid and exclusive.

4. The computer system of claim 2 , wherein the cache access request can be completed locally if the cache access request is a write and the state of the cache corresponding to the cache access request is valid and owned.

5. The computer system of claim 1 , wherein the cache access request is associated with an identifier.

6. The computer system of claim 5 , wherein the identifier is maintained after the transaction has completed locally.

7. The computer system of claim 6 , wherein the identifier is maintained until all expected probe responses from the second cluster are received.

8. The computer system of claim 7 , wherein the identifier is a transaction identifier

memory access serialization point is a memory controller in the second cluster.

9. A computer system, comprising:

a first cluster including a first plurality of processors and a first cache coherence controller, the first plurality of processors and the first cache coherence controller interconnected in a point-to-point architecture;

a second cluster including a second plurality of processors and a second cache coherence controller, the second plurality of processors and the second cache coherence controller interconnected in a point-to-point architecture, the first cache coherence controller coupled to the second cache coherence controller and constructed to receive a cache access request originating from the first plurality of processors, send a probe to the first plurality of processors in the first cluster and send the cache access request to the second cluster, wherein the probe and the cache access request are sent to the first plurality of processors at substantially the same time.

10. A cache coherence controller, the cache coherence controller comprising:

interface circuitry coupled to a plurality of local processors in a local cluster and a non-local cache coherence controller in a non-local cluster, wherein the plurality of local processors are arranged in a point-to-point architecture;

a protocol engine coupled to the interface circuitry, the protocol engine configured to receive a cache access request from a first processor in the local cluster and speculatively probe a local node, wherein the protocol engine forwards the cache access request before receiving a probe response from the local node associated with the cache.

11. The cache coherence controller of claim 10 , wherein the protocol engine forwards the cache access request before determining if the cache access request can be completed locally.

12. The cache coherence controller of claim 11 , wherein the cache access request can be completed locally if the cache access request is a read and the state of the cache corresponding to the cache access request is valid.

13. The cache coherence controller of claim 11 , wherein the cache access request can be completed locally if the cache access request is a write and the state of the cache corresponding to the cache access request is valid and exclusive.

14. The cache coherence controller of claim 11 , wherein the cache access request can be completed locally if the cache access request is a write and the state of the cache corresponding to the cache access request is valid and owned.

15. The cache coherence controller of claim 11 , wherein the cache access requests is associated with an identifier.

16. The cache coherence controller of claim 15 , wherein the identifier is maintained after the transaction has completed locally.

17. The cache coherence controller of claim 16 , wherein the identifier is maintained until all expected probe responses from non-local nodes associated with non-local clusters are received.

18. The cache coherence controller of claim 17 , wherein the identifier is a transaction identifier.

19. The cache coherence controller of claim 10 , wherein speculatively probing the local node comprises sending a probe to the local node before a memory line associated the probe is locked.

20. The cache coherence controller of claim 19 , wherein the plurality of local processors in the local cluster share a memory address space with a plurality of non-local processors in the non-local cluster.

21. The cache coherence controller of claim 19 , wherein speculatively probing a local node comprises sending a probe to the local node associated with a cache before a request associated with the probe is received at a memory access serialization point.

22. The cache coherence controller of claim 21 , wherein the memory access serialization point is a memory controller in the non-local cluster.

23. The cache coherence controller of claim 10 , further comprising determining if speculative probing of the local node can be performed.

24. The cache coherence controller of claim 23 , wherein determining if speculative probing can be performed comprises verifying that a memory line associated with the cache access request is not locked.

25. A method for a cache coherence controller to manage data access in a multiprocessor system, the method comprising:

receiving a cache access request from a local processor associated with a local cluster of processors connected through a point-to-point architecture;

determining if speculative probing of a local node associated with a cache can be performed before forwarding the cache request to a non-local cache coherence controller, the non-local cache coherence controller associated with a remote cluster of processors connected through a point-to-point architecture, wherein the remote cluster of processors shares an address space with the local cluster of processors;

sending the cache access request before receiving a probe response from the local node associated with the cache.

26. The method of claim 25 , wherein the cache access request can be completed locally if the cache access request is a read and the state of the cache corresponding to the cache access request is valid.

27. The method of claim 25 , wherein the cache access request can be completed locally if the cache access request is a write and the state of the cache corresponding to the cache access request is valid and exclusive.

28. The method of claim 25 , wherein the cache access request can be completed locally if the cache access request is a write and the state of the cache corresponding to the cache access request is valid and owned.

29. The method of claim 25 , wherein the cache access requests is associated with an identifier.

30. The method of claim 29 , wherein the identifier is maintained after the transaction has completed locally.

31. The method of claim 30 , wherein the identifier is maintained until all expected probe responses from non-local nodes associated with non-local clusters are received.

32. The method of claim 31 , wherein the identifier is a transaction identifier.

33. The method of claim 25 , wherein speculatively probing the local node comprises sending a probe to the local node before a memory line associated the probe is locked.

34. The method of claim 25 , wherein the plurality of local processors in the local cluster share a memory address space with a plurality of non-local processors in the non-local cluster.

35. The method of claim 25 , wherein speculatively probing a local node comprises sending a probe to the local node associated with a cache before a request associated with the probe is received at a memory access serialization point.

36. The method of claim 35 , wherein the memory access serialization point is a memory controller in the non-local cluster.

37. An apparatus for managing data access in a multiprocessor system, the method comprising:

means for receiving a cache access request from a local processor associated with a local cluster of processors connected through a point-to-point architecture;

means for determining if speculative probing of a local node associated with a cache can be performed before forwarding the cache request to a non-local cache coherence controller, the non-local cache coherence controller associated with a remote cluster of processors connected through a point-to-point architecture, wherein the remote cluster of processors shares an address space with the local cluster of processors;

means for sending the cache access request before receiving a probe response from the local node associated with the cache.

38. The apparatus of claim 37 , wherein the cache access request can be completed locally if the cache access request is a read and the state of the cache corresponding to the cache access request is valid.

39. The apparatus of claim 37 , wherein the cache access request can be completed locally if the cache access request is a write and the state of the cache corresponding to the cache access request is valid and exclusive.

40. The apparatus of claim 37 , wherein the cache access request can be completed locally if the cache access request is a write and the state of the cache corresponding to the cache access request is valid and owned.

41. The apparatus of claim 37 , wherein the cache access requests is associated with an identifier.

42. The apparatus of claim 41 , wherein the identifier is maintained after the transaction has completed locally.

43. The apparatus of claim 42 , wherein the identifier is maintained until all expected probe responses from non-local nodes associated with non-local clusters are received.

44. The apparatus of claim 43 , wherein the identifier is a transaction identifier.

45. The apparatus of claim 37 , wherein speculatively probing the local node comprises sending a probe to the local node before a memory line associated the probe is locked.

46. The apparatus of claim 37 , wherein the plurality of local processors in the local cluster share a memory address space with a plurality of non-local processors in the non-local cluster.

47. The apparatus of claim 37 , wherein speculatively probing a local node comprises sending a probe to the local node associated with a cache before a request associated with the probe is received at a memory access serialization point.

48. The apparatus of claim 47 , wherein the memory access serialization point is a memory controller in the non-local cluster.

49. A method for a cache coherence controller to manage data access in a multiprocessor system, the method comprising:

receiving a cache access request originating from a first cluster of processors;

sending a probe to nodes associated with the first cluster of processors;

sending the cache access request to a second cluster of processors;

wherein sending the probe and the cache access request occur at substantially the same time.

50. The method of claim 49 , wherein the cache coherence controller is constructed to act as an aggregate remote cache.

51. The method of claim 49 , wherein the cache coherence controller is constructed to act as a probing agent pair.

52. The method of claim 49 , wherein the cache coherence controller is constructed to act as a remote memory.

53. The method of claim 49 , wherein the cache coherence controller is constructed to act as a remote processor.