Error checking and correcting for content addressable memories (CAMs)
View Patent ↗Error checking and correcting (ECC) is performed on data held in a content addressable memory. An error check circuit receives words from a memory circuit or circuits, generates an error status and generates a corrected value when appropriate. A control circuit sequences through each of the words of the memory circuit(s), periodically reads from the memory circuit the next word in the sequence and provides the next word to the error check circuit. The bandwidth consumed by the periodic error check phase can be controlled by adjusting the interval between reads.
1. An error control system for use within a content addressable memory, comprising:
a first and second memory circuit type, the first memory circuit type storing an address value of a value stored by the second memory circuit type;
a first and second error check circuit corresponding to the first and second memory circuit type, the first and second error check circuit concurrently implementing an error correcting code determining whether an error has occurred in the address and the value; and
a control circuit configured to periodically invoke the first and second error check circuit.
2. The error control system of claim 1 , wherein a rate of the periodic invoking is adjustable.
3. The error control system of claim 1 , wherein:
the first and second error check circuit is further configured to detect a correctable error in the address value and the value; and
the control circuit is further configured to write the corrected value back into the respective memory circuit type when the correctable error is detected.
4. The error control system of claim 1 , wherein:
the first and second error check circuits are configured to detect an uncorrectable error in the address value and the value, respectively; and
the control circuit is configured to activate an external error signal when the uncorrectable error is detected.
5. The error control system of claim 1 , further comprising:
a third memory circuit type, the third memory circuit type configured to store a compressed representation of the address value.
6. The error control system of claim 1 , wherein the error correcting code is selected from a Hamming code, a single error detection code, a double error detection code, a single error correction code and a single error correct double error detection (SECDED) code.
7. The error control system of claim 1 , wherein:
the first memory circuit type is a compare memory, the address value stored in the compare memory being prioritized relative to other stored address values.
8. The error control system of claim 7 , wherein a priority of the address value in the compare memory is given by an address within the compare memory of the address value.
9. A method of checking for errors in a content addressable memory, comprising:
holding a multiplicity of words in a content addressable memory, each word having a plurality of bits; and
alternating between an access phase of an address stored in the content addressable memory and an error check phase of the address stored in the content addressable memory, the error check phase comprising:
i) sequencing through each of the words;
ii) reading a next word in the sequence; and
iii) generating an error status from the next word.
10. The method of claim 9 , wherein the error check phase has an adjustable duty cycle.
11. The method of claim 9 , further comprising:
detecting a correctable error in the next word,
generating a corrected value for the next word when the correctable error is detected; and
writing the corrected value back into the content addressable memory when the correctable error is detected.
12. The method of claim 9 , further comprising:
detecting an uncorrectable error in the next word; and
activating an external signal when the uncorrectable error is detected.
13. The method of claim 9 , wherein the error check phase occurs concurrently within each of a plurality of memories.
14. The method of claim 9 , further comprising:
accessing the addressable memory for a lookup operation, wherein some words in the content addressable memory have priority over other words in the content addressable memory; and
invalidating a result of the lookup operation, when the lookup process matches a word with a priority less than the priority of a word of the compare memory that has an uncorrectable error.
15. The method of claim 9 , wherein the error check phase accounts for between about 3% and about 5% of a total time allocated to the error check phase and the access phase.
16. The method of claim 9 , wherein the error check phase and the access phase sequence through a pipeline of operations.
17. The method of claim 16 , wherein the pipeline of operations includes,
determining an address value stored within a key compare memory; and
locating a value having the address represented by the address within a value memory.
18. A content addressable memory, comprising:
at least one memory means for holding a multiplicity of words, each word having a plurality of bits;
at least one checking means for receiving a particular word and for generating an error status from the particular word; and
a control means for alternating between an access phase of the content addressable memory and an error check phase of the content addressable memory
wherein an amount of the alternating is controlled through a register setting.
19. The content addressable memory of claim 18 , further comprising:
a register having a setting controlling an amount of time between error check phases.
20. The content addressable memory of claim 19 , wherein the look up pipeline sequences through a key compare memory to determine an address value for a value located within a value memory.
21. The content addressable memory of claim 18 , wherein the access phase and the error check phase are executed through a look up pipeline.