Method of manufacturing an array substrate for a liquid crystal display device
View Patent ↗An advantage of the present invention is to provide a method of manufacturing an array substrate for a liquid crystal display device in which a mask that has double slits in it is used in the photolithographic masking process for the pixel electrode to reduce the distance between a pixel electrode and a neighboring pixel electrode and thus reduce the width of a data line, which results in an improvement of the aperture ratio.
1. A manufacturing method of an array substrate for a liquid crystal display device, comprising:
forming a gate line and a gate electrode on a substrate;
forming a gate insulating layer on the substrate;
forming an active layer and an ohmic contact layer on the gate insulating layer;
forming a data line, a source electrode and a drain electrode on the substrate;
forming a passivation layer by forming insulating material on the substrate;
forming a drain contact hole by patterning the passivation layer, the drain contact hole exposing a part of the drain electrode;
forming a transparent metal layer on the passivation layer;
forming a photo-resist layer on the transparent metal layer;
performing a light exposure process by disposing a mask over the photo-resist layer formed on the transparent metal layer, the mask including a light blocking portion, a slit portion and a light transmission portion, the slit portion corresponding to the data line; and
forming a pixel electrode by developing the photo-resist layer exposed to light through the mask and etching the exposed transparent metal layer.
2. The method according to claim 1 , wherein the light blocking portion of the mask corresponds to the pixel electrode, the light transmission portion of the mask corresponds to the active layer, the source electrode and the drain electrode and the slit portion corresponds to the data line.
3. The method according to claim 1 , wherein a distance between the pixel electrode and a neighboring pixel electrode is 2 to 3.5 μm.
4. The method according to claim 1 , wherein a width of the data line is 6 to 7.5 μm.
5. A method of manufacturing an array substrate for a liquid crystal display device, comprising:
forming a gate line and a gate electrode on a substrate;
forming a gate insulating layer on the substrate;
forming an active layer and an ohmic contact layer on the gate insulating layer;
forming a data line, a source electrode and a drain electrode on the substrate;
forming a passivation layer by forming an insulating material on the substrate;
forming a drain contact hole by patterning the passivation layer, the drain contact hole exposing a part of the drain electrode;
forming a transparent metal layer on the passivation layer;
forming a photo-resist layer on the transparent metal layer;
performing a light exposure by disposing a mask over the photo-resist layer, the mask including a light blocking portion, a slit portion having at least two slits and a light transmission portion; and
forming a pixel electrode by developing the photo-resist layer exposed to light and etching the exposed transparent metal layer.
6. The method according to claim 5 , wherein a width of the slit is 1.2 μm.
7. The method according to claim 5 , wherein a distance between the slit and the neighboring slit is 0.5 μm.
8. A manufacturing method of a thin film transistor array substrate for a display device, comprising:
forming a plurality of gate lines and a plurality of gate electrodes on a substrate by depositing and etching a first conductive layer;
forming a gate insulating layer on the substrate to cover the plurality of gate lines and the plurality of gate electrodes;
forming a plurality of island-shaped active layers and a plurality of island-shaped ohmic contact layers on the gate insulating layer;
forming a plurality of data lines, a plurality of source electrodes and a plurality of drain electrodes on the gate insulating layer, on the plurality of active layers and on the plurality of ohmic contact layers by depositing and etching a second conductive layer;
forming a passivation layer having a plurality of contact holes for exposing at least one of the conductive layers by depositing and etching an insulating material on the gate insulating layer to cover the plurality of data lines, the plurality of source electrodes and the plurality of drain electrodes; and
forming a plurality of pixel electrodes overlapping with the plurality of data lines and having a space less than 3.5 μm between at least two neighboring pixel electrodes on the passivation layer.
9. The method according to claim 8 , wherein a distance between the pixel electrode and the neighboring pixel electrode is 2 to 3.5 μm.
10. The method according to claim 8 , wherein a width of the data line is 6 to 7.5 μm.
11. The method according to claim 8 , wherein the plurality of pixel electrodes is formed to utilize a mask including a light blocking portion, a slit portion and a light transmission portion.
12. The method according to claim 11 , wherein the light blocking portion of the mask corresponds to the pixel electrode, the light transmission portion of the mask corresponds to the active layer, the source electrode and the drain electrode and the slit portion corresponds to the data line.
13. A method of manufacturing a thin film transistor array substrate for a display device, comprising:
forming a plurality of gate lines and a plurality of gate electrodes on a substrate by depositing and etching a first conductive layer;
forming a gate insulating layer on the substrate to cover the plurality of gate lines and the plurality of gate electrodes;
forming a plurality of island-shaped active layers and a plurality of island-shaped ohmic contact layers on the gate insulating layer;
forming a plurality of data lines, a plurality of source electrodes and a plurality of drain electrodes on the gate insulating layer, on the plurality of active layers and on the plurality of ohmic contact layers by depositing and etching a second conductive layer;
forming a passivation layer having a plurality of contact holes for exposing at least one of the conductive layers by depositing and etching an insulating material on the gate insulating layer to cover the plurality of data lines, the plurality of source electrodes and the plurality of drain electrodes; and
forming a plurality of pixel electrodes overlapping with the plurality of data lines and having a space of less than 3.5 μm between at least two neighboring pixel electrodes on the passivation layer, and the plurality of pixel electrodes is formed to utilize a mask including a light blocking portion, a slit portion having at least two slits and a light transmission portion.
14. The method according to claim 13 , wherein a width of the slit is 1.2 μm.
15. The method according to claim 13 wherein the distance between the slit and the neighboring slit is 0.5 μm.
16. The method according to claim 5 , wherein the photo-resist layer is formed on the transparent metal layer.
17. The method according to claim 5 , wherein a distance between the pixel electrode and a neighboring pixel electrode is 2 to 3.5 μm.
18. The method according to claim 5 , wherein an overlap between the pixel electrode and both sides of the data line is less than 2 μm.