IP Library Granted Patent US 7,577,192
Granted Patent B2
US 7,577,192 · App. 10/109,753 · Granted Aug 18, 2009

Method and apparatus for characterizing the distortion produced by electronic equipment

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Quick Facts
Patent No.
US 7,577,192
App. No.
10/109,753
Granted
Aug 18, 2009
Kind
B2
Abstract

Methods and apparatus for evaluating the performance of electronic components and systems by minimizing or eliminating intersymbol interference (ISI). The apparatus includes a transmitter, a device under test, a receiver, and at least one electrical connection between the transmitter and receiver that bypasses the device under test. The electrical connection between the transmitter and receiver transmits information characterizing the intersymbol interference of the transmitted signal to the receiver. The receiver includes an equalizer that uses the information characterizing the intersymbol interference of the transmitted signal to minimize or eliminate intersymbol interference in the received signal wherein the distortion introduced by the device under test can be isolated and characterized. The methods and devices can be used to evaluate the performance of data transmission systems and components, for example, software models of high-speed data transmission systems, and, among other things, reduces the need for fabricating prototype hardware for testing.

Claims (27)

1. A method for characterizing the distortion produced by an electronic device in a system simulator, comprising:

generating a first electrical signal by a correlator/integrator having at least some intersymbol interference;

transmitting the first electrical signal through an equalizer having a first delay element to a signal processor, the equalizer having at least one source of signal distortion;

generating a second electronic signal containing at least some data characterizing the first electrical signal;

transmitting the second electrical signal received by the signal processor;

processing the first electrical signal received by the signal processor and the second electrical signal via a plurality of multipliers to produce a third electrical signal containing less intersymbol interference than the first electrical signal received by the signal processor; and

providing at least some data characterizing the intersymbol interference of the first signal to the signal processor.

2. The method as recited in claim 1 , where processing the first electrical signal received by the signal processor and the second electrical signal to produce a third electrical signal comprises using at least some of the data characterizing the intersymbol interference of the first electrical signal.

3. The method as recited in claim 1 , where the equalizer is an electronic system.

4. The method as recited in claim 3 , where the electronic system is a high speed data transmission system.

5. The method as recited in claim 1 , where transmitting the second electrical signal is practiced via a dedicated electrical connection between a transmitter and the signal processor.

6. The method as recited in claim 1 , where processing the first electrical signal and the second electrical signal is practiced where the third electrical signal contains at least about 90% less intersymbol interference than the first electrical signal received by the signal processor.

7. The method as recited in claim 1 , where further comprising comparing the third electrical signal to the first electrical signal to characterize the source of distortion in the equalizer.

8. A method of processing electrical signals having at least some intersymbol interference in a system simulator, comprising:

generating a first electrical signal by a correlation/integrator having at least some intersymbol interference;

transmitting the first electrical signal through an equalizer having a first delay element over a channel to a signal processor, the channel having at least one source of signal distortion;

generating a second electrical signal containing at least some data characterizing the first electrical signal;

transmitting the second electrical signal to the signal processor;

processing the first electrical signal and the second electrical signal via a plurality of multipliers to produce a third electrical signal containing less intersymbol interference than the first electrical signal received by the signal processor; and

providing at least some data characterizing the intersymbol interference of the first signal to the signal processor.

9. The method as recited in claim 8 , where processing the first electrical signal and the second electrical signal to produce a third electrical signal comprising at least some of the data characterizing the intersymbol interference of the first electrical signal.

10. The method as recited in claim 8 , where the channel comprises an electronic device and the method tests the distortion produced by the electronic device.

11. The method as recited in claim 10 , where the electronic device is a high speed data transmission device.

12. The method as recited in claim 11 , where the high speed data transmission device is a software model of a communications system.

13. The method as recited in claim 8 , where transmitting the second electrical signal comprises transmitting the second electrical signal via a dedicated electrical connection between a transmitter and the signal processor.

14. The method as recited in claim 8 , where the third electrical signal contains at least about 90% less intersymbol interference than the first signal received by the signal processor.

15. The method as recited in claim 8 , further comprising comparing the third electrical signal to the first electrical signal to characterize the source of distortion in the channel.

Assignments (5)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Feb 8, 2024
From: AWR LLC
To: CADENCE DESIGN SYSTEMS, INC.
Reel/Frame 066414/0891 →
RELEASE OF SECURITY INTEREST IN PATENTS (REEL/FRAME 057280/0028) Recorded Oct 13, 2023
From: WELLS FARGO BANK, NATIONAL ASSOCIATION, AS ADMINISTRATIVE AGENT
To: NATIONAL INSTRUMENTS CORPORATION
Reel/Frame 065231/0466 →
RELEASE OF SECURITY INTEREST IN PATENTS (REEL/FRAME 052935/0001) Recorded Oct 13, 2023
From: WELLS FARGO BANK, NATIONAL ASSOCIATION, AS ADMINISTRATIVE AGENT
To: NATIONAL INSTRUMENTS CORPORATION; PHASE MATRIX, INC.
Reel/Frame 065653/0463 →
SECURITY INTEREST Recorded Jun 18, 2021
From: NATIONAL INSTRUMENTS CORPORATION
To: WELLS FARGO BANK, NATIONAL ASSOCIATION
Reel/Frame 057280/0028 →
SECURITY INTEREST Recorded Jun 14, 2020
From: NATIONAL INSTRUMENTS CORPORATION; PHASE MATRIX, INC.
To: WELLS FARGO BANK, NATIONAL ASSOCIATION
Reel/Frame 052935/0001 →