Methods and apparatus for equalization in single-ended chip-to-chip communication
View Patent ↗Disclosed are novel methods and apparatus for efficiently providing equalization in single-ended chip-to-chip communication. In an embodiment, a method of adjusting signal levels to provide improved communication between a sender device and a receiver device is disclosed. The method includes providing a plurality of voltage dividers. The plurality of voltage dividers may be coupled to each other to provide a reference voltage to the receiver device. The method further includes providing a storage device to store previously received data by the receiver device and providing a controller to selectively activate the plurality of voltage dividers.
1. A method of adjusting signal levels to provide improved communication between a sender device and a receiver device, the method comprising:
providing a plurality of voltage dividers, the plurality of voltage dividers coupled to each other to provide a reference voltage to the receiver device;
providing a storage device to store a data pattern comprising at least two data bits of the same value transmitted from the sender device to the receiver device; and
providing a controller to selectively activate the plurality of voltage dividers, wherein the controller receives the data pattern from the storage device; and
wherein the reference voltage is adjusted based on the stored data pattern comprising at least two data bits of the same value transmitted from the sender device.
2. The method of claim 1 wherein the adjustment of the reference voltage improves a diminished voltage margin present during transmission of lonely 0's.
3. The method of claim 1 wherein the adjustment of the reference voltage improves a diminished voltage margin present during transmission of lonely 1's.
4. The method of claim 1 wherein 1's and wherein the reference voltage is adjusted relatively lower than a nominal value when the stored data pattern includes a series of 0's.
5. The method of claim 1 wherein when one voltage divider of the plurality of voltage dividers is activated other voltage dividers of the plurality of voltage dividers are deactivated.
6. The method of claim 1 wherein the controller; comprises an XOR gate, an AND gate and a NOR gate;
the plurality of voltage dividers includes a first voltage divider coupled to the XOR gate, a second voltage divider coupled to the AND gate and a third voltage divider coupled to the NOR gate;
wherein the XOR gate activates the first voltage divider when the stored data pattern includes a 1 and a 0 and the reference voltage is adjusted to a nominal value, the AND gate activates the second voltage divider when the stored data pattern includes at least two 1's and the reference voltage is adjusted relatively higher than a nominal value, and the NOR gate activates the third voltage divider when the stored data pattern includes at least two 0's and the reference voltage is adjusted relatively lower than a nominal value.
7. The method of claim 1 wherein the storage device is implemented within the receiver device.
8. The method of claim 1 wherein the storage device includes a plurality of FIFOs.
9. The method of claim 1 wherein the plurality of voltage dividers include items selected from a group comprising a pull up resistor, a pull down resistor, and a transistor.
10. The method of claim 1 wherein the receiver device is a CMOS device.
11. The method of claim 1 wherein the sender device is a CMOS device.
12. An apparatus for adjusting signal levels to provide improved communication between a sender device and a receiver device, the apparatus comprising:
a plurality of voltage dividers, the plurality of voltage dividers coupled to each other to provide a reference voltage to the receiver device;
a storage device to store a data pattern comprising at least two data bits of the same value transmitted from the sender device to the receiver device; and
a controller to selectively activate the plurality of voltage dividers, wherein the controller receives the data pattern from the storage device; and
wherein the reference voltage is adjusted based on the stored data pattern comprising at least two data bits of the same value transmitted from the sender device.
13. The apparatus of claim 12 wherein the adjustment of the reference voltage improves a diminished voltage margin present during transmission of lonely 0's.
14. The apparatus of claim 12 wherein the adjustment of the reference voltage improves a diminished voltage margin present during transmission of lonely 1's.
15. The apparatus of claim 12 wherein the reference voltage is adjusted relatively higher than a nominal value when the data pattern includes a series of 1's and wherein the reference voltage is adjusted relatively lower than a nominal value when the data pattern includes a series of 0's.
16. The apparatus of claim 12 wherein when one voltage divider of the plurality of voltage dividers is activated other voltage dividers of the plurality of voltage dividers are deactivated.
17. The apparatus of claim 12 wherein the controller comprises an XOR gate, an AND gate and a NOR gate;
the plurality of voltage dividers includes a first voltage divider coupled to the XOR gate, a second voltage divider coupled to the AND gate and a third voltage divider coupled to the NOR gate;
wherein the XOR gate activates the first voltage divider when the stored data pattern includes a 1 and a 0 and the reference voltage is adjusted to a nominal value, the AND gate activates the second voltage divider when the stored data pattern includes at least two 1's and the reference voltage is adjusted relatively higher than a nominal value, and the NOR gate activates the third voltage divider when the stored data pattern includes at least two 0's and the reference voltage is adjusted relatively lower than a nominal value.
18. The apparatus of claim 12 wherein the storage device is implemented within the receiver device.
19. The apparatus of claim 12 wherein the storage device includes a plurality of FIFOs.
20. The apparatus of claim 12 wherein the plurality of voltage dividers include items selected from a group comprising a pull up resistor, a pull down resistor, and a transistor.
21. The apparatus of claim 12 wherein the receiver device is a CMOS device.
22. The apparatus of claim 12 wherein the sender device is a CMOS device.
23. An apparatus comprising:
communication means to provide communication between a sending means and a receiving means;
voltage dividing means to provide a reference voltage to the receiving means;
storage means to store a data pattern comprising at least two data bits of the same value transmitted from the sender device to the receiving means; and
controller means to receive the data pattern from the storage means and selectively activate a plurality of voltage dividers within the voltage dividing means to adjust the reference voltage based on the data pattern.
24. The apparatus of claim 23 wherein the storage means is implemented within the receiving means.