Sampling mechanism including instruction filtering
View Patent ↗A sampling mechanism is disclosed in which software can specify a property or properties which characterize samples of interest. For example, if the software is interested in cache behavior, the software can specify that information for memory operations, or only information for memory instructions which miss in one or more caches, be reported. The sampling mechanism may specify many such properties and events (properties and events may vary from processor to processor, and may also depend on which properties or events are considered useful for performance analysis).
1. A method of sampling instructions executing in a processor comprising:
setting a candidate counter to a number
selecting an instruction for sampling;
storing information relating to the instruction after the instruction is selected for sampling, the information relating to the instruction including information relating to execution of the instruction;
determining whether all events for the instruction have occurred;
determining whether the instruction includes events of interest, the events of interest being based upon the information relating to execution of the instruction;
decrementing the candidate counter when all events for the instruction have occurred and
when the instruction includes events of interest;
determining whether the candidate counter equals zero;
reporting the instruction when the candidate counter equals zero; and,
repeating the setting, selecting, storing, determining whether all events for the instruction have occurred, determining whether the instruction includes events of interest, decrementing and reporting, such that while information is stored relating to a plurality of instructions, then information relating to an instruction is only reported for instructions containing events of interest.
2. The method of claim 1 further comprising
providing a register with a bit vector representing events of interest; and wherein
the determining whether the instruction includes events of interest further includes comparing the information relating to the instruction to the bit vector.
3. The method of claim 1 wherein the comparing is via at least one of a mask operation or a more expressive operation.
4. The method of claim 1 wherein
the information relating to the instruction represents an instruction history, and
the instruction history includes information relating to at least one of an events value, a
program counter value, a branch target address value, an effective memory address value, a latency value, a number in issue bundle value, a number in retire bundle value, a privileged value, a branch history value and a number in fetch bundle value.
5. The method of claim 1 wherein
the selecting an instruction for sampling is based upon sample selection criteria; and
the sample selection criteria include information relating to at least one of an interesting event value, a program counter range value, a latency mask value, and a privileged, non-privileged value.