Semiconductor device and method of manufacturing the same
View Patent ↗To improve a reflow characteristic and realize leadlessness. A semiconductor device comprises a cross die pad which supports a semiconductor chip and in which an area of the region joined to the semiconductor chip is smaller than that of the outer size thereof being smaller than the rear surface of the semiconductor chip; wires connected to pads of the semiconductor chip; a plurality of inner leads which are arranged around the semiconductor chip and in which a silver plating layer is formed at a wire bonding area; molding resin for resin sealing the semiconductor chip; a plurality of outer leads exposed from the molding resin and in which a lead-free metallic layer is formed on a contact surface, wherein the flat surface size of the molding resin is formed to be equal to or less than 28 mm×28 mm and the thickness thereof is formed to be 1.4 mm or less, and thereby it is possible to improve a reflow characteristic and realize leadlessness.
1. A semiconductor device comprising:
a cross-shaped die pad supporting a semiconductor chip and being smaller in outer size than a rear surface of said semiconductor chip which is connected to said die pad with a plurality of small double-sided adhesive tapes;
a wire connected to a surface electrode of said semiconductor chip;
a plurality of inner leads located around said semiconductor chip, in which a silver plating layer is formed at a wire bonding area of at least one of the inner leads to which said wire is bonded,
a molding resin for resin sealing said semiconductor chip; and
a plurality of outer leads respectively connected to the inner leads and protruding from the molding resin, in which a lead-free metallic layer is formed on a contact surface,
wherein the flat surface size of said molding resin is formed to be equal to or less than 28 mm×28 mm and the thickness thereof is formed to be 1.4 mm or less; and
wherein said lead-free metallic layer formed on said outer leads is a metallic layer formed after bonding said wire to said wire bonding area of said at least one inner lead.
2. The semiconductor device according to claim 1 , wherein said lead-free metallic layer is a solder plating layer having a fusion point higher than tin-lead eutectic solder.
3. The semiconductor device according to claim 1 , wherein said lead-free metallic layer is a metallic layer formed after forming said molding resin.