Protection circuit for preventing unauthorized access to the memory device of a processor
View Patent ↗A protection circuit ( 1 ) is coupled to a processor ( 2 ) and a memory device ( 3 ) which preferably form a physical unit, and prevents unauthorized access to the memory device ( 3 ) by combining internal and/or external signals (s 2 , s 3 , s 4 ; s 1 ) in a logic device ( 5 ) for detecting the unauthorized access. These signals are control signals of the processor-memory system and correspond to the status of the latter. In the event of an unauthorized memory access, the logic device ( 5 ) disables an externally accessible data interface ( 6 ) and/or inhibits the control signals (s 5 ) necessary for access to the memory device ( 3 ).
1. A protection circuit which is coupled to a processor and a memory device, and prevents unauthorized access to the memory device, wherein in order to detect an unauthorized memory access, comprising internal and external signals serving to control the processor and the memory device or signaling the respective operational status of the processor and the memory device are applied to a logic device, and wherein, if an unauthorized memory access is detected, the logic device will inhibit the unauthorized memory access, wherein the inhibition of the memory access is effected by inhibiting at least one signal for memory control and/or by disabling an externally accessible data interface.
2. The protection circuit of claim 1 , wherein the unauthorized external memory access relates to a read function and/or a write function to be protected in the entire memory device or in individual memory areas, with the write function to be protected including the protection of memory contents against unauthorized erasure.
3. The protection circuit of claim 2 , wherein each memory area is assigned a separate access authorization.
4. The protection circuit of claim 1 , wherein the respective memory areas are defined by area signals, and that the memory areas are each linked with an access authorization.
5. The protection circuit of claim 1 , wherein the access authorization for the respective memory area is contained as a read or write access authorization in a memory protection control register.
6. The protection circuit of claim 5 , wherein the memory protection control register is located in a protected area (Bi) of the memory device.
7. The protection circuit of claim 1 , wherein in the logic device, a read or write instruction (RE, WE) initiated by the processor is combined with other internal or external signals.
8. The protection circuit of claim 1 , wherein in the logic device, access signals for activating the externally accessible data interface are combined with other internal or external signals.
9. The protection circuit of claim 4 , wherein in the logic device, the area signal is combined with other internal or external signals.
10. The protection circuit of claim 1 , wherein in the logic device, an instruction cycle status signal or data cycle status signal is combined with other internal or external signals.