IP Library Granted Patent US 6,920,588
Granted Patent B1
US 6,920,588 · App. 10/119,223 · Granted Jul 19, 2005

Transmitting data in a communication network

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Quick Facts
Patent No.
US 6,920,588
App. No.
10/119,223
Granted
Jul 19, 2005
Kind
B1
Abstract

Transmitting data includes receiving a serial sequence of code words. Each code word includes a word and check bits, where the word includes a sequence of word symbols, and the check bits includes a sequence of check bit symbols. The following is repeated until a last word symbol of a last code word is reached: selecting a next code word, and inserting a next word symbol of the selected code word into a vector. The following is repeated until a last check bit symbol of the last code word is reached: selecting a next code word, and inserting a next check bit symbol of the selected code word into the vector. The vector is transmitted.

Claims (98)

1. A method for transmitting data, comprising:

receiving a serial sequence of words, each word comprising a sequence of word symbols;

generating a plurality of check bits for each word according to a parallel process, the check bits comprising a sequence of check bit symbols, the plurality of check bits for a word providing for error correction for the word;

forming a serial sequence of code words, each code word comprising a word and a plurality of check bits;

repeating until a last word symbol of a last code word is reached:

selecting a next code word; and

inserting a next word symbol of the selected code word into a next slot of a vector;

repeating until a last check bit symbol of the last code word is reached:

selecting a next code word; and

inserting a next check bit symbol of the selected code word into a next slot of the vector; and

transmitting the vector.

2. The method of claim 1 , further comprising:

receiving the vector;

generating a syndrome for a word using the check bits associated with the word; and

detecting an error of the word according to the syndrome.

3. The method of claim 1 , further comprising:

receiving the vector;

generating a syndrome for a word using the check bits associated with the word, the syndrome comprising a portion describing an error pattern, the error pattern describing how to correct an error of a word symbol of the word; and

performing an operation on the word symbol and the error pattern to correct the error of the word symbol according to the error pattern.

4. The method of claim 1 , further comprising:

receiving the vector;

generating a syndrome for a word using the check bits associated with the word; and

identifying a word symbol of the word having an error according to a portion of the syndrome, the portion directly identifying the word symbols having the error.

5. A system for transmitting data, comprising:

an input operable to receive a serial sequence of words, each word comprising a sequence of word symbols;

at least one check bit generator coupled to the input and operable to generate a plurality of check bits for each word according to a parallel process, the check bits comprising a sequence of check bit symbols, the plurality of check bits for a word providing for error correction for the word;

at least one symbol shuffler coupled to the check bit generator and operable to:

form a serial sequence of code words, each code word comprising a word and a plurality of check bits;

repeat until a last word symbol of a last code word is reached:

selecting a next code word; and

inserting a next word symbol of the selected code word into a next slot of a vector; and

repeat until a last check bit symbol of the last code word is reached:

selecting a next code word; and

inserting a next check bit symbol of the selected code word into a next slot of the vector; and

an output coupled to the symbol shuffler and operable to transmit the vector.

6. The system of claim 5 , further comprising at least one syndrome generator operable to:

receive the vector;

generate a syndrome for a word using the check bits associated with the word; and

detect an error of the word according to the syndrome.

7. The system of claim 5 , further comprising:

at least one syndrome generator operable to:

receive the vector;

generate a syndrome for a word using the check bits associated with the word, the syndrome comprising a portion describing an error pattern, the error pattern describing how to correct an error of a word symbol of the word; and

at least one error corrector coupled to the syndrome generator and operable to performing an operation on the word symbol and the error pattern to correct the error of the word symbol according to the error pattern.

8. The system of claim 5 , further comprising:

at least one syndrome generator operable to:

receive the vector;

generate a syndrome for a word using the check bits associated with the word; and

at least one lookup table coupled to the syndrome generator and operable to identify a word symbol of the word having an error according to a portion of the syndrome, the portion directly identifying the word symbols having the error.

9. A logic for transmitting data, the logic encoded in a medium and operable to:

receive a serial sequence of words, each word comprising a sequence of word symbols;

generate a plurality of check bits for each word according to a parallel process, the check bits comprising a sequence of check bit symbols, the plurality of check bits for a word providing for error correction for the word;

form a serial sequence of code words, each code word comprising a word and a plurality of check bits;

repeat until a last word symbol of a last code word is reached:

selecting a next code word; and

inserting a next word symbol of the selected code word into a next slot of a vector;

repeat until a last check bit symbol of the last code word is reached:

selecting a next code word; and

inserting a next check bit symbol of the selected code word into a next slot of the vector; and

transmit the vector.

10. The logic of claim 9 , wherein the logic is further operable to:

receive the vector;

generate a syndrome for a word using the check bits associated with the word; and

detect an error of the word according to the syndrome.

11. The logic of claim 9 , wherein the logic is further operable to:

receive the vector;

generate a syndrome for a word using the check bits associated with the word, the syndrome comprising a portion describing an error pattern, the error pattern describing how to correct an error of a word symbol of the word; and

performing an operation on the word symbol and the error pattern to correct the error of the word symbol according to the error pattern.

12. The logic of claim 9 , wherein the logic is further operable to:

receive the vector;

generate a syndrome for a word using the check bits associated with the word; and

identify a word symbol of the word having an error according to a portion of the syndrome, the portion directly identifying the word symbols having the error.

13. A method for transmitting data, comprising:

means for receiving a serial sequence of words, each word comprising a sequence of word symbols;

means for generating a plurality of check bits for each word according to a parallel process, the check bits comprising a sequence of check bit symbols, the plurality of check bits for a word providing for error correction for the word;

means for forming a serial sequence of code words, each code word comprising a word and a plurality of check bits;

means for repeating until a last word symbol of a last code word is reached:

selecting a next code word; and

inserting a next word symbol of the selected code word into a next slot of a vector;

means for repeating until a last check bit symbol of the last code word is reached:

selecting a next code word; and

inserting a next check bit symbol of the selected code word into a next slot of the vector; and

means for transmitting the vector.

14. A method for transmitting data, comprising:

receiving a serial sequence of words, each word comprising a sequence of word symbols;

generating a plurality of check bits for each word according to a parallel process, the check bits comprising a sequence of check bit symbols, the plurality of check bits for a word providing for error correction for the word;

generating a serial sequence of code words from the serial sequence of words according to a parallel process, each code word comprising a word and a plurality of check bits;

repeating until a last word symbol of a last code word is reached:

selecting a next code word; and

inserting a next word symbol of the selected code word into a next slot of a vector;

repeating until a last check bit symbol of the last code word is reached:

selecting a next code word; and

inserting a next check bit symbol of the selected code word into a next slot of the vector;

transmitting the vector;

receiving the vector;

generating a syndrome for a word using the check bits associated with the word, the syndrome comprising a first portion describing an error pattern, the error pattern describing how to correct an error of a word symbol of the word;

identifying the word symbol of the word having the error according to a second portion of the syndrome, the second portion directly identifying the word symbols having the error; and

performing an operation on the word symbol and the error pattern to correct the error of the word symbol according to the error pattern.

Assignments (4)
RELEASE OF SECURITY INTEREST Recorded Jan 21, 2015
From: BANK OF AMERICA, N.A., AS ADMINISTRATIVE AGENT
To: BROCADE COMMUNICATIONS SYSTEMS, INC.; INRANGE TECHNOLOGIES CORPORATION; FOUNDRY NETWORKS, LLC
Reel/Frame 034792/0540 →
SECURITY AGREEMENT Recorded Dec 22, 2008
From: BROCADE COMMUNICATIONS SYSTEMS, INC.; FOUNDRY NETWORKS, INC.; INRANGE TECHNOLOGIES CORPORATION; MCDATA CORPORATION
To: BANK OF AMERICA, N.A. AS ADMINISTRATIVE AGENT
Reel/Frame 022012/0204 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Dec 19, 2007
From: SANERA SYSTEMS, INC.
To: BROCADE COMMUNICATIONS SYSTEMS, INC.
Reel/Frame 020271/0577 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Apr 8, 2002
From: YANG, LIUXI (NMI); FANG, YU (NMI); STERN, ULRICH (NMI); CHAMDANI, JOSEPH I.
To: SANERA SYSTEMS INC.
Reel/Frame 012792/0088 →