Digital delay lock loop for setup and hold time enhancement

1. A delay lock loop (DLL) circuit for an N-bit datapath, comprising:

a clock loop, including a clock variable delay unit (VDU) for receiving and delaying a clock signal, a data VDU for receiving and delaying the clock signal, a phase detector configured to measure a phase difference between the delayed clock signals, a filter/control circuit for adjusting the delay of the clock VDU to align the clock signal to within an eye opening of each one of a plurality of at least partially parallel data signals, and a lock circuit for generating a lock signal when the clock signal is aligned; and

N data loops, each data loop being enabled by the lock signal and including a clock VDU for receiving and delaying the clock signal, a data VDU for receiving and delaying one of N at least partially-coincident parallel data signals being time-shifted from each other, a phase detector configured to measure a phase difference between the delayed clock signal and the delayed data signal, the filter/control circuit for adjusting the delay of the data VDU to align the data signal with the adjusted delayed clock signal, and a demultiplexer for outputting the aligned data signal and adjusted delayed clock signal.

2. The DLL circuit of claim 1 , wherein each filter/control circuit includes a nonlinear digital filter.

3. The DLL circuit of claim 1 , wherein the N data loops are configured to remove the time-shift from the N parallel data signals.

4. The DLL circuit of claim 3 , wherein the N data loops are configured to decrease a speed of each of the N parallel data signals.

5. A delay lock loop (DLL) circuit for an N-bit datapath, comprising:

a clock loop, comprising:

a clock signal input;

a clock variable delay unit (VDU) having a first input coupled to the clock signal input, and a delayed clock signal output;

a data VDU having an input coupled to the clock signal input;

a phase detector having a first input coupled to the delayed clock signal output, and a second input coupled to an output of the data VDU;

a filter/control circuit having an input coupled to an output of the phase detector, and a first output connected to a second input of the clock VDU;

a lock circuit having an input coupled to a second output of the filter/control circuit, and a lock detection signal output; and

N data loops, each data loop comprising:

a clock signal input;

a data signal input;

a clock VDU having an input coupled to the clock signal input, and a delayed clock signal output;

a data VDU having a first input coupled to the data signal input, and a delayed data signal output;

a phase detector having a first input coupled to the delayed clock signal output, and a second input coupled to the delayed data signal output;

a filter/control circuit having an input coupled to an output of the phase detector, and an output connected to a second input of the data VDU; and

a demultiplexer having a first input coupled to the delayed clock signal output and a second input coupled to the delayed data signal output, and having demultiplexed clock and data outputs.

6. The DLL circuit of claim 5 , wherein each filter/control circuit includes a nonlinear digital filter.

7. A digital delay lock loop (DLL) circuit for an N-bit datapath, comprising:

a clock DLL configured to provide a clock signal pulse within an eye opening of each of N data signals; and

N data DLLs, each being configured to adjust a delay of one of the N data signals to substantially center the eye opening of the data signal on the clock signal pulse,

wherein the clock DLL comprises:

a clock signal input;

a clock variable delay unit (VDU) having a first input coupled to the clock signal input, and a delayed clock signal output:

a data VDU having an input coupled to the clock signal input;

a phase detector having a first input coupled to the delayed clock signal output, and a second input coupled to an output of the data VDU;

a filter/control circuit having an input coupled to an output of the phase detector, and a first output connected to a second input of the clock VDU;

a lock circuit having an input coupled to a second output of the filter/control circuit, and a lock detection signal output; and,

wherein each data DLL comprises:

a clock signal input;

a data signal input;

a clock VDU having an input coupled to the clock signal input, and a delayed clock signal output;

a data VDU having a first input coupled to the data signal input, and a delayed data signal output;

a phase detector having a first input coupled to the delayed clock signal output, and a second input coupled to the delayed data signal output;

a filter/control circuit having an input coupled to an output of the phase detector, and an output connected to a second input of the data VDU; and

a demultiplexer having a first input coupled to the delayed clock signal output and a second input coupled to the delayed data signal output, and having demultiplexed clock and data outputs.

8. The circuit of claim 7 , wherein the filter/control circuit includes a nonlinear digital filter.