Device for processing data by means of a plurality of processors

1. A data processing device comprising a plurality of processors that are to access a memory system, comprising:

at least two memories included in said memory system;

one bus per memory;

at least one bridge interconnecting the buses;

a processor connected to a bus; and

at least one memory table specifying with which memory an exchange of a data item between a processor and the memory system must be effected;

wherein plural non-conflicting memory accesses, including accesses through said bridge, are executed simultaneously.

2. A data processing device as claimed in claim 1 , further comprising an arbiter which is intended to define an order of priority of access to a memory among the at least two memories in a case where several processors wish to access said memory simultaneously.

3. A method for exchanging a data item between a processor and two or more memories, comprising:

accessing a memory table to determine a particular memory included in the two or more memories to read the data item from or to write the data item to;

transmitting the data item over a first bus associated with the processor;

transmitting the data item over at least one bridge; and

transmitting the data item over a second bus associated with the memory, wherein the at least one bridge interconnects the first bus to the second bus;

wherein plural non-conflicting memory accesses, including accesses through said bridge, are executed simultaneously.