IP Library Granted Patent US 6,972,265
Granted Patent B1
US 6,972,265 · App. 10/122,737 · Granted Dec 6, 2005

Metal etch process selective to metallic insulating materials

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Quick Facts
Patent No.
US 6,972,265
App. No.
10/122,737
Granted
Dec 6, 2005
Kind
B1
Abstract

A method is provided which includes patterning one or more metal layers arranged above a metal insulating layer and terminating the patterning process upon exposure of the metal insulating layer. In particular, the method may be adapted to be more selective to the metal insulating layer than the one or more metal layers. In general, such an adaptation may include exposing the semiconductor topography to an etch chemistry comprising hydrogen bromide. In some cases, the etch chemistry may further include a fluorinated hydrocarbon. In yet other embodiments, the method may further or alternatively include using a reactive ion etch process, etching at a relatively low temperature, using a resist mask, and/or using an etch chemistry substantially absent of an oxygen plasma. In this manner, the method may, in some embodiments, include patterning the one or more metal layers using a reactive ion etch process substantially absent of an oxygen plasma.

Claims (19)

1. A method for processing a semiconductor topography, comprising:

depositing a tunneling layer above one or more underlying magnetic layers;

depositing one or more overlying magnetic layers above the tunneling layer;

patterning the one or more overlying magnetic layers with an etch chemistry comprising HBr to form an upper portion of a magnetic cell junction; and

terminating the step of patterning upon exposing the tunneling layer.

2. The method of claim 1 , further comprising patterning a resist mask above the one or more overlying magnetic layers prior to the step of patterning the one or more overlying magnetic layers.

3. The method of claim 1 , further comprising:

depositing an interlevel dielectric above the tunneling layer; and

etching a via within the interlevel dielectric to expose a portion of the tunneling layer.

4. The method of claim 1 , wherein the one or more overlying magnetic layers comprises nickel-iron.

5. The method of claim 1 , wherein the tunneling layer comprises aluminium oxide.

6. The method of claim 1 , wherein the step of patterning is conducted at a temperature between approximately 20° C. and approximately 120° C.

7. The method of claim 1 , further comprising:

depositing a cap layer above the one or more overlying magnetic layers; and

depositing a resist mask above the cap layer prior to the step of patterning the one or more overlying magnetic layers.

8. The method of claim 1 , wherein the etch chemistry further comprises a fluorinated hydrocarbon.

9. The method of claim 8 , wherein the fluorinated hydrocarbon comprises CF 4 .

10. The method of claim 9 , wherein the etch chemistry comprises a HBr:CF4 ratio between approximately 2:1 and approximately 4:1.

11. The method of claim 1 , wherein the step of patterning comprises a reactive ion etch process.

Assignments (5)
CORRECTIVE ASSIGNMENT TO CORRECT THE 8647899 PREVIOUSLY RECORDED ON REEL 035240 FRAME 0429. ASSIGNOR(S) HEREBY CONFIRMS THE SECURITY INTERST. Recorded Nov 3, 2020
From: CYPRESS SEMICONDUCTOR CORPORATION; SPANSION LLC
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 058002/0470 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Dec 14, 2016
From: CYPRESS SEMICONDUCTOR CORPORATION
To: MONTEREY RESEARCH, LLC
Reel/Frame 040911/0238 →
PARTIAL RELEASE OF SECURITY INTEREST IN PATENTS Recorded Aug 11, 2016
From: MORGAN STANLEY SENIOR FUNDING, INC., AS COLLATERAL AGENT
To: CYPRESS SEMICONDUCTOR CORPORATION; SPANSION LLC
Reel/Frame 039708/0001 →
SECURITY INTEREST Recorded Mar 21, 2015
From: CYPRESS SEMICONDUCTOR CORPORATION; SPANSION LLC
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 035240/0429 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jul 8, 2010
From: SILICON MAGNETIC SYSTEMS
To: CYPRESS SEMICONDUCTOR CORPORATION
Reel/Frame 024651/0158 →