Command issuing apparatus for high-speed serial interface

1. A command issuing apparatus as an initiator in a high-speed serial interface for issuing a command to a target by using a packet, comprising:

a sequence control circuit activated by a central processing unit (CPU) for controlling a command issue sequence;

a packet processing circuit for assembling operation request blocks (ORB) to be issued into a transmission packet and extracting a status from a received packet;

a command ORB transmission buffer for storing a command ORB provided by said CPU;

a management ORB transmission buffer for storing a management ORB provided by said CPU;

a status reception buffer for management for storing a status received for an issued management ORB and providing the status to said CPU; and

a status reception buffer for command for storing a status received for an issued command ORB and providing the status to said CPU,

wherein said command ORB transmission buffer has a capacity for storing a plurality of command ORBs at a time, and

wherein said command ORB transmission buffer automatically assigns and rewrites an address into a next_ORB field so that a plurality of ORBs to be stored are linked even if the next_ORB field is null.

2. A command issuing apparatus as an initiator in a high-speed serial interface for issuing a command to a target by using a packet, comprising:

a sequence control circuit activated by a central processing unit (CPU) for controlling a command issue sequence;

a packet processing circuit for assembling operation request blocks (ORB) to be issued into a transmission packet and extracting a status from a received packet;

a command ORB transmission buffer for storing a command ORB provided by said CPU;

a management ORB transmission buffer for storing a management ORB provided by said CPU;

a status reception buffer for management for storing a status received for an issued management ORB and providing the status to said CPU; and

a status reception buffer for command for storing a status received for an issued command ORB and providing the status to said CPU,

wherein said command ORB transmission buffer has a capacity for storing a plurality of command ORBs at a time, and

wherein said command ORB transmission buffer rewrites the next_ORB field to link the ORBs, and then requests said sequence control circuit to access a DOORBELL register of said target when a new command ORB is stored during the execution of a command ORB; and

said sequence control circuit generates and issues a packet accessing said DOORBELL register in response to the request from said command ORB transmission buffer.

3. A command issuing apparatus as an initiator in a high-speed serial interface for issuing a command to a target by using a packet, comprising:

a sequence control circuit activated by a central processing unit (CPU) for controlling a command issue sequence;

a packet processing circuit for assembling operation request blocks (ORB) to be issued into a transmission packet and extracting a status from a received packet;

a command ORB transmission buffer for storing a command ORB provided by said CPU;

a management ORB transmission buffer for storing a management ORB provided by said CPU;

a status reception buffer for management for storing a status received for an issued management ORB and providing the status to said CPU; and

a status reception buffer for command for storing a status received for an issued command ORB and providing the status to said CPU,

wherein said command ORB transmission buffer, by itself, automatically assigns and rewrites an address into a next_ORB field without an operation of the CPU.

4. A command issuing apparatus as an initiator in a high-speed serial interface for issuing a command to a target by using a packet, comprising:

a sequence control circuit activated by a central processing unit (CPU) for controlling a command issue sequence;

a packet processing circuit for assembling operation request blocks (ORB) to be issued into a transmission packet and extracting a status from a received packet; and

a command ORB transmission buffer for storing a plurality of command ORBs provided by said CPU at a time;

wherein said command ORB transmission buffer, by itself, assigns and rewrites an address into a next_ORB field of command ORB which is stored in the end of said command ORB transmission buffer so that a plurality of ORBs are linked when the CPU issues an additional command ORB during an execution of a plurality of linked command ORB.

5. A command issuing apparatus as an initiator in a high-speed serial interface for issuing a command to a target by using a packet, comprising:

a sequence control circuit activated by a central processing unit (CPU) for controlling a command issue sequence;

a packet processing circuit for assembling operation request blocks (ORB) to be issued into a transmission packet and extracting a status from a received packet; and

a command ORB transmission buffer for storing a plurality of command ORBs provided by said CPU at a time;

wherein said command ORB transmission buffer rewrites a next_ORB field of a command ORB in said command ORB buffer from null to an address of a new command ORB to link the ORBs, and then requests said sequence control circuit to access a DOORBELL register of said target when the new command ORB is stored during the execution of a command ORB; and

said sequence control circuit generates and issues a packet accessing said DOORBELL register in response to the request from said command ORB transmission buffer.