Sea-of-cells array of transistors
View Patent ↗The invention concerns integrated circuits in which a MACRO is embedded in a standard cell array. One level of metal is devoted exclusively to non-local interconnect, and a layer of polysilicon is devoted to local interconnect, thereby saving significant space.
1. An integrated circuit, comprising:
a plurality of inverters in a standard cell array, the standard cell array having a plurality of cells, wherein each of said inverters is disposed in one of the plurality of cells of said standard cell array and each of said plurality of cells is of the same width;
a plurality of MACROs wherein at least one of said plurality of MACROs comprises a cell having a cell width different from a cell width of said plurality of cells of said standard cell array in which each of said inverters is disposed; and
a second layer of metallization;
wherein said second layer of metallization comprises;
a signal connection between at least two of said MACROs; and
no local interconnect for any of said inverters.
2. The integrated circuit as described in claim 1 , and further comprising:
no local interconnect within said second layer of metallization in at least one of said MACROS.
3. The integrated circuit as described in claim 1 , and further comprising:
no local interconnect within said second layer of metallization in a plurality of said MACROS.
4. The integrated circuit as described in claim 1 and further comprising:
no local interconnect within said second layer of metallization in all of said plurality of MACROs.
5. The integrated circuit as described in claim 1 , wherein said standard cell array comprises a row pitch and at least one MACRO has a row pitch equivalent to the row pitch of said standard cell array.