IP Library Granted Patent US 6,961,040
Granted Patent B2
US 6,961,040 · App. 10/126,318 · Granted Nov 1, 2005

Two-dimensional monochrome bit face display

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Quick Facts
Patent No.
US 6,961,040
App. No.
10/126,318
Granted
Nov 1, 2005
Kind
B2
Abstract

A two-dimensional monochrome bit face display has a luminance resolution that is equal to or higher than that of a CRT monitor. In one implementation, a two-dimensional monochrome bit face display has a bit face in which each pixel is constituted by m sub-pixels and neutral density filters mounted on the m sub-pixels of a respective pixel have light transmittances proportional to values ½ n where n is an integer. In another implementation, mask filters are mounted on the m sub-pixels and have windows with light transmittances that are proportional to values ½ n . Alternatively, areas of the m sub-pixels are set in the same proportion. The luminance of each sub-pixel is electronically controlled to improve the luminance resolution of the bit face display.

Claims (58)

1. A two-dimensional monochrome bit face display having a bit face in which each pixel is constituted by three sub-pixels, the display comprising:

a neutral density filter having a light transmittance substantially equal to 50% that is mounted on one or two sub-pixels of the three sub-pixels constituting each of a plurality of respective pixels;

an input circuit that receives an image signal and a control command;

m sub-pixel luminance control circuits that output luminance control signals for controlling luminances of the m sub-pixels constituting the plurality of respective pixels;

m rewritable look-up table circuits each coupled to an input of a respective sub-pixel luminance control circuit to supply predetermined luminance information to the respective sub-pixel luminance control circuit;

a look-up table control circuit that controls content of look-up tables written into the m look-up table circuits; and

a control circuit that controls luminance of the bit face on the basis of luminance control signals outputted by the m sub-pixel luminance control circuits.

2. The two-dimensional monochrome bit face display as set forth in claim 1 , wherein the bit face display is a liquid crystal display.

3. The two-dimensional monochrome bit face display as set forth in claim 1 comprising a time base control circuit that varies the luminance of sub-pixels between two frames of an image on said display to present the image with an apparent luminance resolution that is greater than the luminance resolution of either frame of the image.

4. The two-dimensional monochrome bit face display as set forth in claim 3 , wherein the bit face display is a liquid crystal display.

5. A two-dimensional monochrome bit face display having a bit face in which each pixel is constituted by three sub-pixels, the display comprising:

a mask filter having a window with light transmittance substantially equal to 50% that is mounted on one or two of the three sub-pixels constituting each of a plurality of respective pixels;

an input circuit that receives an image signal and a control command;

m sub-pixel luminance control circuits that output luminance control signals for controlling luminances of the m sub-pixels constituting the plurality of respective pixels;

m rewritable look-up table circuits each coupled to an input of a respective sub-pixel luminance control circuit to supply predetermined luminance information to the respective sub-pixel luminance control circuit;

a look-up table control circuit that controls content of look-up tables written into the m look-up table circuits; and

a control circuit that controls luminance of the bit face on the basis of luminance control signals outputted by the m sub-pixel luminance control circuits.

6. The two-dimensional monochrome bit face display as set forth in claim 5 , wherein the bit face display is a liquid crystal display.

7. The two-dimensional monochrome bit face display as set forth in claim 5 , comprising a time base control circuit that varies the luminance of sub-pixels between two frames of an image on said display to present the image with an apparent luminance resolution that is greater than the luminance resolution of either frame of the image.

8. The two-dimensional monochrome bit face display as set forth in claim 7 , wherein the bit face display is a liquid crystal display.

9. A two-dimensional monochrome bit face display having a bit face in which each pixel is constituted by m sub-pixels, where m is an integer equal to or greater than 3, the display comprising:

two or more filters that are mounted on at least some of the m sub-pixels constituting each of a plurality of respective pixels, wherein the filters are neutral density filters having relative light transmittances proportional to values substantially equal to (½) n where n is an integer;

an input circuit that receives an image signal and a control command;

m sub-pixel luminance control circuits that output luminance control signals for controlling luminances of the m sub-pixels constituting the plurality of respective pixels;

m rewritable look-up table circuits each coupled to an input of a respective sub-pixel luminance control circuit to supply predetermined luminance information to the respective sub-pixel luminance control circuit;

a look-up control circuit that controls content of look-up tables written into the m look-up table circuits; and

a control circuit that controls luminance of the bit face on the basis of luminance control signals outputted by the m sub-pixel luminance control circuits.

10. The two-dimensional monochrome bit face display as set forth in claim 9 wherein m neutral density filters are mounted on the m sub-pixels of a respective pixel and n is an integer from 0 to m−1.

11. The two-dimensional monochrome bit face display as set forth in claim 10 , wherein the bit face display is a liquid crystal display and m=3.

12. The two-dimensional monochrome bit face display as set forth in claim 10 comprising a time base control circuit that varies the luminance of sub-pixels between two frames of an image on said display to present the image with an apparent luminance resolution that is greater than the luminance resolution of either frame of the image.

13. The two-dimensional monochrome bit face display as set forth in claim 12 , wherein the bit face display is a liquid crystal display and m=3.

14. The two-dimensional monochrome bit face display as set forth in claim 9 wherein (m−1) neutral density filters are mounted on (m−1) sub-pixels of the m sub-pixels of a respective pixel and n is an integer from 1 to m−1.

15. The two-dimensional monochrome bit face display as set forth in claim 14 , wherein the bit face display is a liquid crystal display and m=3.

16. The two-dimensional monochrome bit face display as set forth in claim 14 comprising a time base control circuit that varies the luminance of sub-pixels between two frames of an image on said display to present the image with an apparent luminance resolution that is greater than the luminance resolution of either frame of the image.

17. The two-dimensional monochrome bit face display as set forth in claim 16 , wherein the bit face display is a liquid crystal display and m=3.

18. The two-dimensional monochrome bit face display as set forth in claim 9 wherein each pixel is constituted by three sub-pixels and three neutral density filters are mounted on the three sub-pixels of a respective pixel having light transmittances proportional to values substantially equal to 100%, 100% and 50%.

19. The two-dimensional monochrome bit face display as set forth in claim 18 , wherein the bit face display is a liquid crystal display.

20. The two-dimensional monochrome bit face display as set forth in claim 18 comprising a time base control circuit that varies the luminance of sub-pixels between two frames of an image on said display to present the image with an apparent luminance resolution that is greater than the luminance resolution of either frame of the image.

21. The two-dimensional monochrome bit face display as set forth in claim 20 , wherein the bit face display is a liquid crystal display.

22. A two-dimensional monochrome bit face display as having a bit face in which each pixel is constituted by m sub-pixels, where m is an integer equal to or greater than 3, the display comprising:

two or more filters that are mounted on at least some of the m sub-pixels constituting each of a plurality of respective pixels, wherein the filters are mask filters having windows with relative light transmittances proportional to values substantially equal to (½) n where n is an integer;

an input circuit that receives an image signal and a control command;

m sub-pixel luminance control circuits that output luminance control signals for controlling luminances of the m sub-pixels constituting the plurality of respective pixels;

m rewritable look-up table circuits each coupled to an input of a respective sub-pixel luminance control circuit to supply predetermined luminance information to the respective sub-pixel luminance control circuit;

a look-up table control circuit that controls content of look-up tables written into the m look-up table circuits; and

a control circuit that controls luminance of the bit face on the basis of luminance control signals outputted by the m sub-pixel luminance control circuits.

23. The two-dimensional monochrome bit face display as set forth in claim 22 wherein m mask filters are mounted on the m sub-pixels of a respective pixel and n is an integer from 0 to m−1.

24. The two-dimensional monochrome bit face display as set forth in claim 23 , wherein the bit face display is a liquid crystal display and m=3.

25. The two-dimensional monochrome bit face display as set forth in claim 23 comprising a time base control circuit that varies the luminance of sub-pixels between two frames of an image on said display to present the image with an apparent luminance resolution that is greater than the luminance resolution of either frame of the image.

26. The two-dimensional monochrome bit face display as set forth in claim 25 , wherein the bit face display is a liquid crystal display and m=3.

27. The two-dimensional monochrome bit face display as set forth in claim 22 wherein (m−1) mask filters are mounted on (m−1) sub-pixels of the m sub-pixel of a respective pixel and n is an integer from 1 to m−1.

28. The two-dimensional monochrome bit face display as set forth in claim 27 , wherein the bit face display is a liquid crystal display and m=3.

29. The two-dimensional monochrome bit face display as set forth in claim 27 comprising a time base control circuit that varies the luminance of sub-pixels between two frames of an image on said display to present the image with an apparent luminance resolution that is greater than the luminance resolution of either frame of the image.

30. The two-dimensional monochrome bit face display as set forth in claim 29 , wherein the bit face display is a liquid crystal display and n=3.

31. The two-dimensional monochrome bit face display as set forth in claim 22 wherein each pixel is constituted by three sub-pixels and three mask filters are mounted on the three sub-pixels of a respective pixel having light transmittances proportional to values substantially equal to 100%, 100% and 50%.

32. The two-dimensional monochrome bit face display as set forth in claim 31 , wherein the bit face display is a liquid crystal display.

33. The two-dimensional monochrome bit face display as set forth in claim 31 comprising a time base control circuit that varies the luminance of sub-pixels between two frames of an image on said display to present the image with an apparent luminance resolution that is greater than the luminance resolution of either frame of the image.

34. The two-dimensional monochrome bit face display as set forth in claim 33 , wherein the bit face display is a liquid crystal display.

Assignments (3)
CHANGE OF NAME Recorded Apr 9, 2014
From: EIZO NANAO CORPORATION
To: EIZO CORPORATION
Reel/Frame 032642/0556 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Aug 4, 2005
From: SPECTRATECH INC.
To: EIZO NANAO CORPORATION
Reel/Frame 016611/0867 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jun 8, 2005
From: SPECTRATECH INC.
To: ENZO NANAO CORPORATION
Reel/Frame 016314/0645 →