System and method for compensating for delay time fluctuations
View Patent ↗A method is provided for time control of data transmission from a first module to a further module. An electronic system also is provided having a first module from which data is sent via a connecting line to a further module, which has a reference signal line via which a reference signal is transmitted from the further module to the first module, which reference signal is chosen as a function of the timing of the data received by the further module, with respect to a clock signal received by the further module. The reference signal has a bit sequence which corresponds to a bit sequence which was received by the further module via the connecting line from the first module.
1. An electronic system for compensating for delay time fluctuations, comprising:
a first module comprising a memory device in which at least some bits of the data
transmitted from the first module to a further module are stored;
a connecting line, wherein the data is transmitted from the first module to the further module via the connecting line; and
a reference signal line via which a reference signal is transmitted from the further module to the first module, wherein the reference signal is selected as a function of a timing of the data received by the further module via the connecting line from the first module, with respect to a clock signal received by the further module, and wherein the reference signal has a bit sequence corresponding to a bit sequence received by the further module via the connecting line from the first module
wherein the transmission of the data by the first module is altered as a function of the reference signal received by the first module, the alteration being one of delaying and speeding up of the data transmission, and wherein an extent of the alteration of the transmission of data is determined based on a comparison of the bits stored in the memory device in the first module with the bit sequence of the reference signal transmitted by the further module to the first module.
2. An electronic system for compensating for delay time fluctuations as claimed in claim 1 , further comprising at least one further connecting line via which the first module transmits further data, in a parallel manner, to the further module.
3. An electronic system for compensating for delay time fluctuations as claimed in claim 2 , wherein the reference signal is chosen as a function of the timing of the data received by the further module via the connecting line and the further data received by the further module via the further connecting line, with respect to the clock signal received by the further module.
4. An electronic system for compensating for delay time fluctuations as claimed in claim 3 , wherein the reference signal has a further bit sequence, which corresponds to a bit sequence received by the further module via the further connecting line from the first module.
5. An electronic system for compensating for delay time fluctuations as claimed in claim 4 , wherein the transmission of further data via the further connecting line is altered by the first module as a function of the further bit sequence, the alteration being one of delaying and speeding up the transmission.
6. An electronic system for compensating for delay time fluctuations as claimed in claim 1 , wherein alteration of the transmission of the data by the first module is chosen as a function of the timing of individual bit, received by the further module, with respect to the clock signal received by the further module.
7. An electronic system for compensating for delay time fluctuations as claimed in claim 6 , wherein the reference signal has at least one bit which identifies whether the individual bit received by the further module has been checked with respect to a time before or after a bit center of the individual bit.
8. An electronic system for compensating for delay time fluctuations as claimed in claim 7 , wherein the individual bit is checked with respect to times defined by the clock signal.
9. An electronic system for compensating for delay time fluctuations as claimed in claim 7 , wherein a logic state of the clock signal at a bit end of the individual bit is determined in order to determine whether the individual bit has been checked with respect to the time before or after the bit center.
10. An electronic system for compensating for delay time fluctuations as claimed in claim 1 , wherein the reference signal also contains parity bits.
11. An electronic system for compensating for delay time fluctuations as claimed in claim 1 , wherein at least one of the first module and the further module includes an integrated circuit.
12. An electronic system for compensating for delay time fluctuations as claimed in claim 11 , wherein the integrated circuit uses CMOS technology.
13. An electronic system for compensating for delay time fluctuations as claimed in claim 11 , wherein the integrated circuit of the further module uses a faster processing speed than the integrated circuit in the first module.
14. An electronic system for compensating for delay time fluctuations as claimed in claim 1 , wherein the first module and the further module are arranged on a same board.
15. An electronic system for compensating for delay time fluctuations as claimed in claim 14 , wherein the first module and the further module are arranged on a same microchip.
16. An electronic system for compensating for delay time fluctuations as claimed in claim 1 , wherein the first module and the further module are arranged on different boards.
17. A method for time control of data transmission from a first module to a further module, the method comprising the steps of:
transmitting data from the first module to the further module via a connecting line;
transmitting a reference signal from the further module to the first module, wherein the reference signal is selected as a function of a timing of the data received by the further module via the connecting line from the first module, with respect to a clock signal received by the further module; and
delaying or speeding up the transmission of the data by the first module as a function of the reference signal received by the first module, wherein an extent of the delaying or speeding up of the transmission of data is determined based on a comparison of the bits stored in a memory device in the first module with a bit sequence of the reference signal transmitted by the further module to the first module.
18. A method for time control of data transmission from a first module to a further module as claimed in claim 17 , wherein the reference signal has a bit sequence corresponding to a bit sequence received by the further module via the connecting line from the first module.