Granted Patent B1

US 7,092,404 · App. 10/128,290 · Granted Aug 15, 2006

Abstract

Claims (32)

1. An interposer chip, having a first side and a second side, the first side having Unilink ports and the second side having DASL ports, the chip comprising:

means for translating data divided into a plurality of data cells from DASL protocol received at DASL ports into Unilink protocol at Unilink ports, and translating data from Unilink protocol received at Unilink ports to DASL protocol at DASL ports, data received in DASL and Unilink protocols being a plurality of data cells in corresponding protocols;

means providing compatibility of Unilink ports with PRIZMA-EQ switch fabric;

means for sub-port flow control;

means providing a capability for DASL ports to support individual ports and link parallel ports;

wherein the means for translating comprises means for providing operation of the chip in one of a line card mode and switch card mode; and

wherein the means for providing operation in the line card mode comprises a first block providing data translation from DASL protocol to Unilink protocol, including:

cell parsing module for arranging cells received at DASL ports in queues;

first cell translation unit for modifying cell headers received from the cell parsing module so as to accommodate Unilink protocol;

ingress buffer manager for managing the modified cells received from the first cell translation module;

ingress buffer for providing storage of the cells received from the ingress buffer manager; and

ingress scheduler for transmitting the cells received from the ingress buffer.

2. An interposer chip as described in claim 1 , wherein the means for providing operation in the line card mode comprises a second block, providing data translation from Unilink protocol into DASL protocol, including:

second cell translation module for modifying cell headers received at Unilink ports so as to accommodate DASL protocol;

egress buffer manager for managing the modified cells received from the second translation unit;

egress buffer for providing storage of the cells received from the egress buffer manager; and

egress scheduler for transmitting the cells received from the egress buffer.

3. An interposer chip as described in claim 1 , wherein the means supporting operation in the switch card mode comprises:

a third block providing data translation from Unilink protocol to DASL protocol, the block including a third cell translation module for modifying cell headers received at Unilink ports so as to accommodate DASL protocol; and

a fourth block providing data translation from DASL protocol to Unilink protocol, the block including a fourth cell translation module for modifying cell headers received at DASL ports so as to accommodate Unilink protocol.

4. A method of translating data, having a plurality of data cells, between DASL and Unilink protocols, comprising the steps of:

translating data in a line card mode; and

translating data in a switch card mode, wherein the step of translating data in the line card mode comprises translating data from DASL protocol into Unilink protocol, including the steps of:

arranging data cells received in DASL protocol into queues according to destination and priority;

modifying data cell headers so as to accommodate Unilink protocol;

managing the modified data cell flow, including storage of data cells; and

transmitting the managed data cell flow.

5. A method as described in claim 4 , wherein the step of translating data in the line card mode comprises translating data from Unilink protocol into DASL protocol, including the steps of:

modifying data cell headers received in Unilink protocol so as to accommodate DASL protocol;

managing the modified data cell flow including storage of data cells; and

transmitting the managed data cell flow.

6. A method as described in claim 4 , wherein the step of translating data in the switch card mode comprises modifying data cell headers so as to accommodate the required protocol.

Assignments (9)