Integrated gigabit ethernet PCI-X controller

1. A network controller, comprising:

a. a multiprotocol bus interface adapter coupled between a communication network and a computer bus, the adapter having:

(1) a clock signal input;

(2) a data delay element interposed in an output data path and imposing a predetermined output data delay upon output data; and

(3) a predictive time base generator coupled with the clock signal input and the data delay element; and

b. an alert supervisory controller coupled with the multiprotocol bus interface adapter, and adapted to monitor and manage preselected components coupled with one of the communication network and the computer bus.

2. The network controller of claim 1 , wherein the computer bus is adapted to employ one of a PCI protocol, a PCI-X protocol, and a combination thereof.

3. The network controller of claim 1 , wherein the network controller is adapted to be a 10/100/1000BASE-T IEEE Std. 802.3-compliant network controller.

4. The network controller of claim 1 , wherein the alert supervisory bus controller is adapted to employ at least one of an Alert Standard Format (ASF) specification protocol, a System Management Bus (SMBus) specification protocol, an Intelligent Platform Management Interface (IPMI) specification protocol, and a Simple Network Management Protocol (SNMP).

5. The network controller of claim 1 , wherein:

a. the multiprotocol bus interface adapter is adapted to employ one of a PCI protocol, a PCI-X protocol, and a combination thereof;

b. the alert supervisory bus controller is adapted to employ at least one of an Alert Standard Format (ASF) specification protocol, a System Management Bus (SMBus) specification protocol, an Intelligent Platform Management Interface (IPMI) specification protocol, and a Simple Network Management Protocol (SNMP); and

c. the network controller is adapted to be a 10/100/1000BASE-T IEEE Std. 802.3-compliant network controller.

6. The network controller of claim 5 , further comprising:

a. a 10/100/1000BASE-T IEEE Std. 802.3-compliant transceiver coupled with the communication network; and

b. a 10/100/1000BASE-T IEEE Std. 802.3-compliant media access controller (MAC) coupled with the transceiver.

7. The network controller of claim 6 , further comprising a buffer memory coupled with the MAC.

8. The network controller of claim 7 , wherein the buffer memory includes one of a packet buffer memory, a frame buffer memory, a queue memory, and a combination thereof.

9. The network controller of claim 7 , further comprising a CPU used to transmit and a CPU used to receive coupled with the multiprotocol bus interface adapter and the alert supervisory bus controller.

10. The network controller of claim 9 , wherein at least one of the multiprotocol computer bus interface adapter and the alert supervisory bus controller further comprises a Gigabit Media Independent Interface (GMII) interface, an 10-Gigabit Media Independent Interface (XGMII), a 10-Gigabit attachment unit interface), XSBI (10-Gigabit serial bus interface (XAUI), a Serial Gigabit Media Independent Interface (SGMII), a Reduced Gigabit Media Independent Interface (RGMII), a Reduced Ten Bit Interface (RTBI), a Ten-Bit Interface (TBI), a Serial Gigabit Media Independent Interface (SMII), and a Media Independent Interface (MII).

11. The network controller of claim 10 , wherein the multiprotocol bus interface adapter interfaces one of an IEEE Std. 802.3-like protocol, a SONET/SDH-like protocol, a Fiber-Channel-like protocol, an SCSI-like protocol, and an InfiniBand-like protocol.

12. The network controller of claim 9 , further comprising a single-chip VLSI device.

13. The network controller of claim 12 , wherein the single-chip VLSI device is an 0.18 micron CMOS VLSI implementation.

14. The network controller of claim 1 wherein the time base generator includes a predictive synchronizer having a synchronizing feedback loop therein.

15. The network controller of claim 14 wherein the time base generator includes a replica delay element coupled with the synchronizing feedback loop and adapted to provide feedback delay substantially replicating the predetermined output data delay, the replica delay element causing the predictive time base generator to provide a predictive clock signal to the data delay element and substantially reducing the predetermined output data delay.

16. A communication system, comprising:

a. a multiprotocol bus interface adapter coupled between a communication network and a computer bus, the adapter having:

(1) a clock signal input;

(2) a data delay element interposed in an output data path and imposing a predetermined output data delay upon output data; and

(3) a predictive time base generator coupled with the clock signal input and the data delay element;

b. an alert supervisory bus controller coupled with the multiprotocol bus interface adapter; adapted to monitor and manage preselected components coupled with one of the communication network and the computer bus; and adapted to employ at least one of an Alert Standard Format (ASF) specification protocol, a System Management Bus (SMBus) specification protocol, an Intelligent Platform Management Interface (IPMI) specification protocol, and a Simple Network Management Protocol (SNMP);

c. a 10/100/1000BASE-T IEEE Std. 802.3-compliant transceiver coupled with the communication network;

d. a 10/100/1000BASE-T IEEE Std. 802.3-compliant media access controller (MAC) coupled with the transceiver;

e. a buffer memory coupled with the MAC, wherein the buffer memory includes one of a packet buffer memory, a frame buffer memory, a queue memory, and a combination thereof; and

f. a CPU used to transmit and a CPU used to receive coupled with the multiprotocol bus interface adapter and the management bus controller to process data respectively transmitted to and received from the computer network;

wherein at least one of the multiprotocol computer bus interface adapter and the alert supervisory bus controller further comprises a Gigabit Media Independent Interface (GMII) interface, an 10-Gigabit Media Independent Interface (XGMII), a 10-Gigabit attachment unit interface), XSBI (10-Gigabit serial bus interface (XAUI), a Serial Gigabit Media Independent Interface(SGMII), a Reduced Gigabit Media Independent Interface (RGMII), a Reduced Ten Bit Interface (RTBI), a Ten-Bit Interface (TBI), a Serial Gigabit Media Independent Interface (SGMII), and a Media Independent Interface (MII), and wherein the multiprotocol bus interface adapter interfaces one of an IEEE Std. 802.3-like protocol, a SONET/SDH-like protocol, a Fiber-Channel-like protocol, an SCSI-like protocol, and an InfiniBand-like protocol.

17. The communication system of claim 16 , further comprising a single-chip VLSI device in an 0.18 micron CMOS VLSI implementation.

18. The communication system of claim 17 , wherein the single-chip VLSI device is implemented in one of a network interface card, and a LAN-on-Motherboard application.

19. A communication system as in claim 16 wherein the time base generator further includes a predictive synchronizer having a synchronizing feedback loop therein.

20. A communication system as in claim 19 wherein the time base generator further includes a replica delay element coupled with the synchronizing feedback loop and adapted to provide feedback delay substantially replicating the predetermined output data delay, the replica delay element causing the predictive time base generator to provide a predictive clock signal to the data delay element and substantially reducing the predetermined output data delay and wherein the computer bus and the multiprotocol bus interface adapter are adapted to employ one of a PCI protocol, a PCI-X protocol, and a combination thereof.