Alerting system, architecture and circuitry
View Patent ↗A method for supporting ASF in an ASD using one or more embedded processors. In one aspect of the invention the method comprises accepting ASF related packets, examining the ASF related packets using a firmware routine running on the one or more embedded processors, and generating a response. It is emphasized that this abstract is provided to comply with the rules requiring an abstract, which will allow a searcher or other reader to quickly ascertain the subject matter of the technical disclosure. It is submitted with the understanding that it will not be used to interpret or limit the scope or the meaning of the claims.
1. A method for supporting ASF (Alert Standard Format) in an ASD (Alert Sending Device) using one or more embedded processors, the method comprising:
receiving a packet stream comprising both ASF and non-ASF packets;
separating the ASF packets from the non-ASF packets;
accepting the ASF related packets to be processed;
examining the accepted ASF related packets using at least one firmware routine running on the one or more embedded processors; and
generating an appropriate response, based on the examination of the accepted ASF related packets.
2. The method of claim 1 , comprising filtering of ASF (Alert Standard Format) packets by comparing packets in the packet stream in a programmable pattern detector.
3. The method of claim 2 , wherein the filtering comprises performing pattern matching using non-processor-based hardware.
4. The method of claim 2 , wherein the filtering comprises performing pattern matching using a state machine.
5. The method of claim 1 , wherein the one or more embedded processors comprise two embedded processors operating in parallel.
6. A method for supporting ASF (Alert Standard Format) in an ASD (Alert Sending Device) using one or more embedded processors, the method comprising:
receiving a packet stream comprising both ASF and non-ASF packets;
separating the ASF packets from the non-ASF packets;
accepting the ASF related packets to be processed;
examining the accepted ASF related packets using a firmware routine running on the one or more embedded processors; and
generating an appropriate response, based on the examination of the accepted ASF related packets,
wherein the one or more embedded processors are running different aspects of the ASF protocol.
7. The method of claim 6 , wherein the examining of the accepted ASF (Alert Standard Format) related packets comprises interpreting a RMCP (Remote Management Control Protocol) packet.
8. The method of claim 7 , wherein the examining of the accepted ASF (Alert Standard Format) related packets comprises interpreting a SMBus message.
9. The method of claim 7 , wherein the examining the accepted ASF (Alert Standard Format) related packets comprises interpreting a ASF packet.
10. The method of claim 7 , wherein the generating of the appropriate response comprises executing a firmware routine that generates a PET (Platform Event Trap) packet.
11. The method of claim 7 , wherein the generating of the appropriate response further comprises executing a firmware routine that generates a RMCP response packet.
12. The method of claim 7 , wherein the generating of the appropriate response comprises executing a firmware routine that generates a SMbus response.
13. A method for processing communications packets in an ASD, the method comprising:
accepting a sequence of packets in an ASD (Alert Sending Device), the sequence of packets comprising a plurality of types of packets;
detecting Remote Management and Control Protocol (RMCP) packets in the accepted sequence of packets, wherein the detecting of the RMCP packets comprises:
accepting the packets in a rules checker; and
comparing the packets to the rules, defining RMCP packets, in the rules checker,
wherein the rules checker is non-processor-based hardware that performs pattern matching;
removing the detected RMCP packets from the sequence of the plurality of types of packets, without affecting or slowing down non RMCP packets within the sequence of packets; and
notifying at least one processor to process the removed RMCP packets.
14. An apparatus for processing communications packets in an ASD (Alert Sending Device), the apparatus comprising:
an input for accepting a sequence of packets in an ASD, the sequence of packets comprising a plurality of types of packets;
a pattern matching circuit for detecting RMCP (Remote Management and Control Protocol) packets within the sequence of packets, wherein the pattern matching circuit is non-processor-based hardware that performs pattern matching; a queue for placing the detected RMCP packets in; and
at least one processor that enables removal of the RMCP packets from the queue and processing the removed RMCP packets.
15. An apparatus for supporting ASF (Alert Standard Format) in an ASD (Alert Sending Device) using one or more embedded processors, the apparatus comprising:
one or more circuits that are operable to:
receive a packet stream comprising both ASF and non-ASF packets;
separate the ASF packets from the non-ASF packets;
accept the ASF related packets to be processed;
examine the accepted ASF related packets using at least one firmware routine running on the one or more embedded processors; and
generate an appropriate response, based on the examination of the accepted ASF related packets.
16. The apparatus of claim 15 , wherein the one or more circuits are operable to filter ASF (Alert Standard Format) packets by comparing packets in the packet stream in a programmable pattern detector.
17. The apparatus of claim 15 , wherein the one or more embedded processors comprise two embedded processors operating in parallel.
18. An apparatus for supporting ASF (Alert Standard Format) in an ASD (Alert Sending Device) using one or more embedded processors, the apparatus comprising:
one or more circuits that are operable to:
receive a packet stream comprising both ASF and non-ASF packets;
separate the ASF packets from the non-ASF packets;
accept the ASF related packets to be processed;
examine the accepted ASF related packets using a firmware routine running on the one or more embedded processors; and
generate an appropriate response, based on the examination of the accepted ASF related packets,
wherein the one or more embedded processors are running different aspects of the ASF protocol.
19. The apparatus of claim 18 , wherein the examining of the accepted ASF (Alert Standard Format) related packets comprises interpreting a RMCP (Remote Management Control Protocol) packet.
20. The apparatus of claim 18 , wherein the examining of the accepted ASF (Alert Standard Format) related packets comprises interpreting a SMBus message.
21. The apparatus of claim 18 , wherein the examining of the accepted ASF (Alert Standard Format) related packets comprises interpreting a ASF packet.
22. The apparatus of claim 18 , wherein the generating of the appropriate response comprises executing a firmware routine that generates a PET (Platform Event Trap) packet.
23. The apparatus of claim 18 , wherein the generating of the appropriate response comprises executing a firmware routine that generates a RMCP response packet.
24. The apparatus of claim 18 , wherein the generating of the appropriate response comprises executing a firmware routine that generates a SMbus response.