Image-signal processing apparatus for clamping analog image signal and then for converting it to digital image signal
View Patent ↗An analog Y signal input from an input terminal 101 is clamped at a pedestal level in a clamp circuit 102 , and then, is converted to a digital image signal in a quantization circuit 103 . The pedestal level Dp of the digital output D(t) 113 is stored in a register 702 . A predetermined value Dref (Dref=0 for the Y signal) is subtracted from Dp in a subtracter 802 . The subtraction output 806 is subtracted from the digital output 113 in a subtracter 803 . The subtraction output 805 (D(t)−(Dp−Dref)) is a signal for which a shift caused by a variation in the precision of the clamp circuit 102 and the quantization circuit 103 has been compensated for. The subtraction output 805 is limited to a predetermined dynamic range by an overflow limiter circuit 807 , and output as Dout.
1. An image-signal processing apparatus comprising:
clamp means for clamping a level of an input image signal to a value close to a predetermined value;
digital conversion means for sampling a clamped image signal and for converting it to a digital image signal; and
calculation means for obtaining the difference between the pedestal level of the digital image signal and the predetermined value and for compensating the digital image signal according to the difference,
wherein the calculation means includes
register means for storing the pedestal level from the output of the digital conversion means;
first calculation means for performing addition or subtraction between the pedestal level stored in the register means and the predetermined value; and
second calculation means for performing addition or subtraction between the output of the digital conversion means and the output of the first calculation means.
2. An image-signal processing apparatus comprising:
clamp means for clamping level of an input image signal to a value close to a predetermined value;
digital conversion means for sampling a clamped image signal and for converting it to a digital image signal; and
calculation means for obtaining the difference between the pedestal level of the digital image signal and the predetermined value and for compensating the digital image signal according to the difference,
wherein the calculation means includes
register means for storing the pedestal level from the output of the digital conversion means;
first calculation means for performing addition or subtraction between the pedestal level stored in the register means and the predetermined value;
switching means for switching between the pedestal level stored in the register means and the output of the digital conversion means, and for outputting switched data; and
second calculation means for performing addition or subtraction between the output of the switching means and the output of the first calculation means.
3. An image-signal processing apparatus according to claim 1 , wherein overflow processing means for limiting the output of the second calculation means to a predetermined range is provided.
4. An image-signal processing apparatus according to claim 1 , wherein the register means comprises:
n(n=2, 3, . . . ) latch means connected in series; and
averaging means for adding the output of the latch means and for dividing the sum by n.
5. An image-signal processing apparatus according to claim 1 , wherein second switching means for switching between the output of the second calculation means and the predetermined value used in calculation by the first calculation means and for outputting switched data is provided after the second calculation means.
6. An image display apparatus comprising an image-signal processing apparatus according to claim 1 .
7. An image-signal processing apparatus according to claim 2 , wherein overflow processing means for limiting the output of the second calculation means to a predetermined range is provided.
8. An image-signal processing apparatus according to claim 2 , wherein the register means comprises:
n(n=2, 3, . . . ) latch means connected in series; and
averaging means for adding the output of the latch means and for dividing the sum by n.
9. An image display apparatus comprising an image-signal processing apparatus according to claim 2 .