High performance architecture with shared memory
View Patent ↗A system with multiple processors sharing a single memory module without noticeable performance degradation is described. The memory module is divided into n independently addressable banks, where n is at least 2 and mapped such that sequential addresses are rotated between the banks. A bank may be further divided into a plurality of blocks. A cache is provided to enable a processor to fetch from memory a plurality of data words from different memory banks to reduce memory latency caused by memory contention.
1. A method of sharing a memory module between a plurality of processors comprising:
dividing the memory module into n banks, where n=at least 2, enabling the memory module to be accessed by one or more processors simultaneously;
mapping the memory module to allocate sequential addresses to alternate banks of the memory module;
storing data words in the memory module, wherein data words in sequential addresses are stored in alternate banks due to the mapping of the memory module;
providing a first signal path, the first signal path coupling a cache to a processor and the memory module when selected, the cache enabling the processor to fetch a plurality of data words from different banks simultaneously;
dividing the bank into x blocks, where x=at least 1, wherein a block can be accessed by one of the plurality of processors at any one time;
determining whether contention has occurred, wherein two or more processors are accessing the same address range at any one time, the address range coincides with at least one block;
synchronizing the processors to access different banks when contention has occurred, wherein the step of synchronizing the processors comprises inserting wait states for processors with lower priorities when contention occurs; and
activating the first signal path when contention has occurred.
2. The method of claim 1 further including the step of providing a second signal path, the second signal path coupling the processor to the memory module when selected.
3. The method of claim 2 further including a step of activating the second signal path when contention has not occurred.
4. The method of claim 3 further including a step of determining access priorities of the processors when contention has occurred.
5. The method of claim 4 wherein the step of determining access priorities comprises assigning lower access priorities to processors that have caused the contention.
6. A system comprising:
a plurality of processors;
a memory module comprising n banks, where n=at least 2, wherein a bank can be accessed by one or more processors at any one time, the bank comprises x blocks, where x=at least 1, wherein a block can be accessed by one of the plurality of processors at any one time;
a memory map for allocating sequential addresses to alternate banks of the memory module;
data words stored in memory, wherein data words in sequential addresses are stored in alternate banks according to the memory map;
a plurality of control logic units for enabling a processor to access a plurality of data words from different banks, wherein a control logic unit comprises first and second signal paths, the first signal path coupling a cache to a processor and the memory module, the second signal path coupling the processor to the memory module, wherein the first signal path comprises a cache register and a multiplexer;
a flow control unit for synchronizing the processors to access different blocks at any one time; and
a priority register for storing the access priority of a processor.
7. The system of claim 6 further comprising a plurality of critical memory modules for storing a plurality of data words for the processors to reduce the possibility of contention.
8. The system of claim 6 wherein a control logic unit comprises a first signal path, the first signal path coupling a cache to a processor and the memory module.