A signal interpolator comprises a fractional interpolator and a numeric controlled oscillator. The numeric controlled oscillator may generate a control signal for controlling the fractional interpolator. The numeric controlled oscillator generally comprises a register, a modulo-M device, and an adder. The register may hold a count value, and the modulo-M device may apply a modulo-M function to the count value to generate the control signal therefrom. The adder may add an increment value to the modulo-M signal from the modulo-M device, to update the count value in the register.
1. A signal interpolator comprising:
a fractional interpolator; and
a numeric controlled oscillator for generating a control signal for controlling said fractional interpolator, said numeric controlled oscillator comprising:
a register for holding a count value;
a modulo-M device for applying a modulo-M function to said count value stored in said register, and generating said control signal therefrom; and
an adder for adding an increment value to said control signal from said modulo-M device, for updating said count value in said register.
2. The signal interpolator according to claim 1 , wherein said adder is configured to add a value STEP to said signal from said modulo-M device, said value STEP being an integer greater than zero.
3. The signal interpolator according to claim 1 , wherein said modulo-M device comprises an overflow signal generator configured to generate an overflow signal when said count value inputted to said modulo-M device overflows said modulo-M function.
4. The signal interpolator according to claim 1 , wherein a value M of said modulo-M device is an integer other than an integer power of two.
5. The signal interpolator according to claim 4 , wherein said value M is an odd number.
6. The signal interpolator according to claim 1 , wherein said signal interpolator is implemented in digital form in an integrated circuit.
7. A digital signal interpolator for converting a first signal comprising digital samples synchronised to a first clock frequency, to a second signal synchronised to a second clock frequency, said signal interpolator comprising:
a fractional interpolator for receiving said digital samples of said first signal synchronised to said first clock frequency; and
a numeric controlled oscillator for generating a control signal for controlling said fractional interpolator, said numeric controlled oscillator comprising:
a modulo-M counter driven by a counter clock frequency being one of said first and said second clock frequencies, said modulo-M counter being configured to (i) repeatedly count through a sequence of count values in a count range of modulus M, where the value M is an integer other than a power of 2, and (ii) generate a modulo-M signal as said control signal for controlling said fractional interpolator.
8. The digital signal interpolator according to claim 7 , wherein the numeric controlled oscillator further comprises:
a period signal generator configured to generate a period signal each time said count value overflows said value M periodically, said period signal being synchronised to one of said first and said second clock frequencies other than said counter clock frequency.
9. The digital signal interpolator according to claim 7 , wherein said counter clock frequency for said modulo-M counter is said first clock frequency to which said first signal is synchronised.
10. The digital signal interpolator according to claim 9 , wherein said numeric controlled oscillator further comprises:
a period signal generator configured to generate a period signal each time said count value overflows said value M periodically, said period signal being synchronised to said second clock frequency.
11. The digital signal interpolator according to claim 7 , wherein said counter clock frequency for said modulo-M counter is said second clock frequency.
12. The digital signal interpolator according to claim 11 , wherein said numeric controlled oscillator further comprises:
a period signal generator configured to generate a period signal each time said count value overflows said value M periodically, said period signal being synchronised to said first clock frequency.
13. The digital signal interpolator according to claim 7 , wherein said modulo-M counter comprises:
a register for holding a count value;
a modulo-M device for applying a modulo-M function to said count value stored in said register; and
an adder for adding an increment value to an output from said modulo-M device, for updating said count value in said register.
14. The digital signal interpolator according to claim 13 , wherein said increment value is a value greater than zero.
15. The digital signal interpolator according to claim 7 , wherein one of said first and said second frequencies is k×13 MHz, where k is an integer between 1 and 10 inclusive.
16. The digital signal interpolator according to claim 7 , wherein one of said first and said second clock frequencies is n×10.24 MHz, where n is an integer between 1 and 10 inclusive.
17. The digital signal interpolator according to claim 7 , wherein said interpolator is incorporated in a quadrature amplitude modulation circuit for adjusting an output timing of said quadrature amplitude modulation circuit.
18. The digital signal interpolator according to claim 7 , wherein said digital signal interpolator is implemented in an integrated circuit.
19. A signal interpolator comprising:
means for performing fractional interpolator in response to a control signal;
means for applying a modulo-M function to a count value for generating said control signal therefrom; and
means for adding an increment value to said control signal for updating said count value.
20. A digital signal interpolator for converting a first signal comprising digital samples synchronised to a first clock frequency, to a second signal synchronised to a second clock frequency, said signal interpolator comprising:
means for receiving said digital samples of said first signal synchronised to said first frequency and for performing fractional interpolation thereon according to a control signal; and
means for counting driven by a counter clock frequency being one of said first and said second clock frequencies, and configured to (i) repeatedly count through a sequence of count values in a count range of modulus M, where the value M is an integer other than a power of 2, and (ii) generate a modulo-M signal as said control signal.
21. A method of interpolating a signal comprising the steps of:
(A) holding a count value;
(B) generating a control signal in response to applying a modulo-M function to said count value;
(C) generating a second signal in response to adding an increment value to said control signal;
(D) updating said count value with said second signal; and
(E) fractional interpolating said signal in response to said control signal.