Chip select method through double bonding
View Patent ↗A chip generally comprising a logic circuit and a plurality of pads. The logic circuit may be configured to operate in a plurality of modes in response to a mode signal. The pads may be configurable into a plurality of subsets such that one of the subsets is used by the logic circuit at a time in response to the mode signal.
1. A chip comprising:
a logic circuit configured to operate in a plurality of non-test modes in response to a mode signal;
a plurality of pads configurable into a plurality of subsets such that one of said subsets is used by said logic circuit at a time in response to said mode signal; and
a switching circuit configured to demultiplex an input signal received through a particular pad of said plurality of pads under control of said mode signal.
2. The chip according to claim 1 , further comprising a first pad circuit configured to drive an output signal onto a first pad of said plurality of pads while enabled by one of a plurality of enable signals multiplexed under control of said mode signal.
3. The chip according to claim 1 , wherein said switching circuit is further configured to multiplex a plurality of first signals to said particular pad under control of said mode signal.
4. The chip according to claim 1 , further comprising:
a first pad circuit directly connected to a first pad of said plurality of pads;
a second pad circuit directly connected to a second pad of said plurality of pads; and
a trace directly routing a signal among said first pad circuit, said second pad circuit and said logic circuit.
5. The chip according to claim 1 , wherein a difference between two of said subsets includes a power pad of said plurality of pads, said power pad providing electrical power to operate said logic circuit.
6. The chip according to claim 5 , further comprising a plurality of said power pads disposed along a side of said chip.
7. The chip according to claim 5 , further comprising:
a mode pad of said plurality of pads (i) adjacent to said power pad and (ii) configured to receive said mode signal from external to said circuit; and
a ground pad of said plurality of pads adjacent to said mode pad, said ground pad providing a ground for said logic circuit.
8. The chip according to claim 5 , wherein an intersection of said two subsets is a non-empty set.
9. The chip according to claim 1 , further comprising a memory configured to store a value used to generate said mode signal.
10. The chip according to claim 1 , wherein said logic circuit comprises a memory map decoder configured to operate with a plurality of memory mappings for a bus internal to said logic circuit based on said mode signal.
11. The chip according to claim 1 , wherein a plurality of said pads from one of said subsets are configured to couple to an external memory in a subset of said modes.
12. The chip according to claim 11 , wherein at least two of said subsets contain a different number of said pads.
13. The chip according to claim 1 , further comprising a first pad circuit configured to receive a first signal from a first pad of said plurality of pads while enabled by one of a plurality of enable signals multiplexed under control of said mode signal.
14. The chip according to claim 1 , wherein said logic circuit is further configured to function as a node for a distributed control network.
15. A chip comprising:
means for generating a mode signal;
means for configuring a logic circuit of said chip to operate in at least three modes in response to said mode signal;
means for configuring a plurality of pads of said chip into a plurality of subsets such that one of said subsets is used by said logic circuit at a time in response to said mode signal; and
means for demultiplexing an input signal received through a first pad of said plurality of pads under control of said mode signal.
16. The chip according to claim 15 , further comprising a package having a plurality of traces connectable to a first subset of said pads to form a first part while said mode signal has a first value.
17. The chip according to claim 16 , wherein said traces are connectable to a second subset of said pads to form a second part unique from said first part while said mode signal has a second value.
18. The chip according to claim 15 , wherein (i) a first subset of said pads are connectable to a plurality of first traces of a first package to form a first part while said mode signal has a first value and (ii) a second subset of said pads are connectable to a plurality of second traces of a second package different than said first package to form a second part unique from said first part while said mode signal has a second value.
19. A chip comprising:
a logic circuit configured to operate in a plurality of modes in response to a mode signal;
a plurality of pads configurable into a plurality of subsets such that one of said subsets is used by said logic circuit at a time in response to said mode signal;
a first pad circuit configured to drive a first pad of said plurality of pads in response to one of a plurality of enable signals determined by said mode signal; and
a switching circuit configured to (i) multiplex a plurality of first signals to said first pad circuit in response to said mode signal and (ii) demultiplex a second signal from said first pad circuit in response to said mode signal.