IP Library Granted Patent US 6,842,067
Granted Patent B2
US 6,842,067 · App. 10/135,490 · Granted Jan 11, 2005

Integrated bias reference

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Quick Facts
Patent No.
US 6,842,067
App. No.
10/135,490
Granted
Jan 11, 2005
Kind
B2
Abstract

An improved integrated bias reference provides a temperature and supply stable bias for devices such as radio frequency amplifiers with less complexity and expense than conventional bias references. The bias reference may be integrated onto a single GaAs die with other active circuitry such as an amplifier.

Claims (32)

1. A bias reference comprising:

an enable supply voltage input;

a constant voltage reference circuit coupled to the enable supply voltage input, the constant voltage reference circuit comprising a proportional-to-absolute-temperature (PTAT) current source summed with a Vbe current source and a constant voltage output referenced to the enable supply voltage input;

a current conveyor circuit coupled to the constant voltage output, the current conveyor circuit comprising an input stage comprising a differential amplifier and an output stage comprising a supply transistor driving a reference transistor; and

a bias reference output coupled to the current conveyor circuit.

2. The bias reference of claim 1 , wherein the constant voltage reference circuit and the current conveyor circuit comprise NPN transistors but no PNP transistors.

3. The bias reference of claim 1 , further comprising a bias adjustment circuit coupled to the current conveyor circuit.

4. The bias reference of claim 3 , wherein the bias adjustment circuit comprises a transistor coupled to a digital to analog converter.

5. The bias reference of claim 1 , wherein the bias reference output couples to a base connection of an amplifier.

6. The bias reference of claim 1 , wherein the supply transistor is an emitter follower transistor with a collector connected to a power supply voltage input.

7. The bias reference of claim 1 , wherein the enable supply voltage is a digital logic input.

8. An integrated bias reference comprising:

a GaAs substrate;

a constant voltage reference circuit fabricated on the substrate and comprising a proportional-to-absolute-temperature (PTAT) current source summed with a Vbe current source and a constant voltage output;

a current conveyor circuit fabricated on the substrate and coupled to the constant voltage output, the current conveyor circuit comprising an input stage comprising a differential amplifier and an output stage comprising a supply transistor driving a reference transistor; and

a bias reference output coupled to the current conveyor circuit.

9. The integrated bias reference of claim 8 , further comprising a bias adjustment circuit fabricated on the substrate and coupled to the current conveyor circuit.

10. The integrated bias reference of claim 9 , wherein the bias adjustment circuit comprises a bias adjustment enable input coupled to a current sink.

11. The integrated bias reference of claim 10 , wherein the bias adjustment enable input comprises a digital logic enable input.

12. The integrated bias reference of claim 10 , wherein the current sink comprises a transistor coupled to the bias adjustment enable input and a resistor coupled to the transistor.

13. The integrated bias reference of claim 8 , wherein the supply transistor is an emitter follower transistor with a collector connected to a power supply input for supplying power supply base current to the reference transistor and the bias reference output.

14. An integrated bias reference comprising:

a GaAs substrate;

a constant voltage reference circuit fabricated on the substrate and comprising a temperature independent voltage output;

an input stage fabricated on the substrate and coupled to the temperature independent voltage output, the input stage comprising a replicated temperature independent voltage node;

a plurality of bias adjustment circuits fabricated on the substrate and coupled to the replicated temperature independent voltage node;

a reference transistor fabricated on the substrate and coupled to the replicated temperature independent voltage node; and

a bias reference output coupled to the reference transistor.

15. The integrated bias reference of claim 14 , wherein each bias adjustment circuit includes a bias adjustment enable input.

16. The integrated bias reference of claim 15 , wherein the constant voltage reference circuit is coupled to an enable supply voltage input.

17. The integrated bias reference of claim 15 , wherein the temperature independent voltage output is referenced to the enable supply voltage input.

18. The integrated bias reference of claim 14 , further comprising a supply transistor fabricated on the substrate and coupled to the reference transistor and to a supply voltage input.