Dynamic switching of parallel termination for power management with DDR memory
View Patent ↗A system and method for managing power consumption of an information handling system dynamically switches between high and low clock speed data transfers with double data rate (DDR) memory. The selection of a high clock speed dynamically switches the DDR memory to connect to a parallel termination for more rapid data transfers with increased power consumption. The selection of a low clock speed dynamically switches the DDR memory to disconnect the parallel termination for slower data transfers with reduced power consumption. In one embodiment, portable computer graphics DDR memory reduces power consumption by selecting low clock speed transfers without parallel termination when operating on internal power. The portable computer graphics DDR memory provides improved display resolution by selecting high clock speed transfers with parallel termination when operating on external power or when displaying information from high resolution applications.
1. A system for managing power consumption in the display of information with internal or external power, the system comprising:
a graphics controller operable to generate first and second display information signals;
a memory device interfaced with the graphics controller, the memory device supporting the generation of the first display information signals by the graphics controller at a first clock speed having a first power consumption level with parallel termination and the second display information signals at a second clock speed having a second power consumption level without parallel termination;
a power consumption manager interfaced with the memory device and operable to switch on parallel termination for display of the information on external power, switch on parallel termination for display of the first display information signals on internal power, and to switch off parallel termination for display of the second display information signals on internal power.
2. The system of claim 1 wherein the internal power source is a battery.
3. The system of claim 1 wherein the first display information is generated by one or more predetermined applications.
4. The system of claim 3 wherein the one or more predetermined applications are high bandwidth display information applications.
5. The system of claim 1 wherein the external power source comprises an alternating current power source.
6. The system of claim 1 wherein the memory device comprises a double data rate memory device.
7. The system of claim 1 wherein the graphics controller comprises a portable computer graphics controller operable to display information through a liquid crystal display.
8. A method for managing power consumption of an information handling system, the method comprising:
determining whether power to the information handling system is supplied by an internal or external power supply;
switching on parallel termination of the graphics controller memory if power is supplied by an external power supply;
switching off parallel termination of the graphics controller memory if power is supplied by an internal power supply; and
switching on parallel termination of the graphics controller memory if power is supplied by an internal power supply and the information handling system is displaying information with a high bandwidth application.
9. The method of claim 8 wherein the information handling system comprises a portable computer.
10. The method of claim 9 wherein the graphics memory comprises double data rate memory having a high and low clock speed, the double data rate memory using parallel termination to operate at the high clock speed.
11. The method of claim 9 wherein the internal power source comprises a battery.
12. The method of claim 9 wherein the external power source comprises an alternating current power source.
13. The method of claim 8 wherein switching on parallel termination further comprises:
sending an on signal from the graphics controller general purpose input/output to a Qswitch; and
activating the Qswitch to interface the graphics memory to the parallel termination.
14. The method of claim 8 wherein switching off parallel termination further comprises:
sending an off signal from the graphics controller general purpose input/output to a Qswitch, and
activating the Qswitch to remove the interface of the graphics memory to the parallel termination.
15. An information handling system comprising:
a central processing unit operable to run applications;
memory interfaced with the central processing unit and operable to communicate information at high and low clock speeds;
a parallel termination interfaced with the memory;
a switch interfaced with the parallel termination and operable to connect or disconnect the memory and the parallel termination;
an internal power source operable to power the memory;
an external power adapter operable to accept external power to power the memory;
a power consumption manager operable to command the switch to connect the parallel termination if the central processing unit runs an application associated with high speed memory communication of information and to disconnect the parallel termination if the central processing unit runs an application associated with low speed memory communication of information during operation with the internal power source.
16. The information handling system of claim 15 further configured as a portable computer.
17. The information handling system of claim 15 wherein the application associated with high speed memory communication of information comprises a high bandwidth graphics application.
18. The information handling system of claim 15 wherein the memory comprises double data rate memory.
19. The information handling system of claim 15 wherein the memory comprises graphics memory and the power consumption manager switches on parallel termination to communicate high bandwidth display information at the high speed.