Flip chip with novel power and ground arrangement
View Patent ↗A flip chip assembly comprising a semiconductor die having a core area and a periphery area. The periphery area including an ESD structure. The semiconductor die includes at least one power conductor to supply power between the core area and the periphery. A substrate is coupled to the semiconductor die via a plurality of electrically conductive bumps. A first connection circuit is located within the semiconductor die core area to couple power between the substrate and the semiconductor die power conductor. An electrically conductive bump provides a connection between the first connection circuit and the substrate. The ESD structure is coupled to the first connection circuit.
1. A flip chip assembly, comprising:
a semiconductor die having a core area and a periphery area, the periphery area including an electrostatic discharge (ESD) structure, and the semiconductor die including at least one power conductor to supply power between the core area and the periphery;
a substrate coupled to the semiconductor die via a plurality of electrically conductive bumps;
a first connection circuit located within the semiconductor die core area to couple power between the substrate and the semiconductor die power conductor, an electrically conductive bump to connect between the first connection circuit and the substrate; and
the ESD structure coupled to the first connection circuit.
2. The flip chip assembly of claim 1 wherein the first connection circuit is selected from the group consisting of bond pads and under ball metallization (UBM).
3. The flip chip assembly of claim 1 further comprising a second connection circuit located over and electrically coupled to the ESD structure; and
the substrate including a first conductive trace to couple the first connection circuit to the second connection circuit such that the ESD structure is coupled to the first connection circuit through the first conductive trace.
4. The flip chip assembly of claim 1 wherein the semiconductor die further comprises a second conductive trace coupled between the first connection circuit and the ESD structure.
5. The flip chip assembly of claim 4 wherein the semiconductor die further comprises a redistribution layer; and
the redistribution layer includes the second conductive trace.
6. The flip chip assembly of claim 1 further including at least a third connection circuit located in the semiconductor die core area to couple power between the substrate and the semiconductor die power conductor, the third connection circuit coupled to the ESD structure.
7. The flip chip assembly of claim 1 wherein the substrate is selected from the group consisting of circuit boards, carriers, and intermediate substrates.
8. A flip chip assembly, comprising:
a semiconductor die having a core area and a periphery area, the periphery area including an electrostatic discharge (ESD) structure, and the semiconductor die including at least one power conductor to supply power between the core area and the periphery;
a substrate coupled to the semiconductor die via a plurality of electrically conductive bumps;
a first under ball metallization (UBM) located within the semiconductor die core area to couple power between the substrate and the semiconductor die power conductor, an electrically conductive bump to connect between the first UBM and the substrate; and
the ESD structure coupled to the first UBM.
9. The flip chip assembly of claim 8 further comprising a second UBM located over and electrically coupled to the ESD structure; and
the substrate including a first conductive trace to couple the first UBM to the second UBM such that the ESD structure is coupled to the first UBM through the first conductive trace.
10. The flip chip assembly of claim 8 wherein the semiconductor die further comprises a second conductive trace coupled between the first UBM and the ESD structure.
11. The flip chip assembly of claim 10 wherein the semiconductor die further comprises a redistribution layer; and
the redistribution layer includes the second conductive trace.
12. The flip chip assembly of claim 8 further including at least a third UBM located in the semiconductor die core area, the third UBM coupled to the ESD structure.
13. The flip chip assembly of claim 8 wherein the substrate is selected from the group consisting of circuit boards, carriers, and intermediate substrates.
14. A flip chip assembly, comprising:
a semiconductor die having a core area and a periphery area, the periphery area including an electrostatic discharge (ESD) means and including at least one means for supplying power;
a substrate coupled to the semiconductor die via a plurality of electrically conductive bumps;
first means for coupling power located within the semiconductor die core area to couple power between the substrate and the semiconductor die power conductor, an electrically conductive bump to connect between the first means for coupling power and the substrate; and
the ESD means coupled to the first means for coupling power.
15. The flip chip assembly of claim 14 further comprising second means for coupling power located over and electrically coupled to the ESD means; and
the substrate including a first conductive trace to couple the first means for coupling power to the second means for coupling power such that the ESD means is coupled to the first means for coupling power through the first conductive trace.
16. The flip chip assembly of claim 14 wherein the semiconductor die further comprises a second conductive trace coupled between the first means for coupling power and the ESD means.
17. The flip chip assembly of claim 16 wherein the semiconductor die further comprises a redistribution layer; and
the redistribution layer includes the second conductive trace.
18. The flip chip assembly of claim 14 further including at least third means for coupling power located in the semiconductor die core area, and the third means for coupling power being coupled to the ESD means.
19. The flip chip assembly of claim 14 wherein the substrate is selected from the group consisting of circuit boards, carriers, and intermediate substrates.