Power efficient booth recoded multiplier and method of multiplication

1. A multiplier circuit, comprising:

a partial product circuit generating a partial product based on outputs of a Booth recoder circuit and a multiplicand, the partial product circuit ANDing the multiplicand with a zero Booth recoded output, the zero Booth recoded output indicating whether to zero out the multiplicand; and

an enable circuit selectively enabling the multiplier circuit, the enable circuit disabling the multiplier circuit by making the zero Booth recoded output indicate to zero out the multiplicand, wherein the enabling circuit ANDs the zero Booth recoded output and an enable signal.

2. The multiplier circuit of claim 1 , wherein the enable circuit holds output of the partial product circuit constant if disabling the partial product circuit.

3. The multiplier circuit of claim 2 , wherein the enable circuit holds the output of the partial product circuit to zero if disabling the partial product circuit.

4. The multiplier circuit of claim 1 , wherein

the partial product circuit generating a partial product based on the multiplicand, the zero Booth recoded output and a negative Booth recoded output, the negative Booth recoded output indicates whether to create a negative partial product; and

the enable circuit disables the multiplier circuit by ANDing the zero Booth recoded output and the neg Booth recoded output with an enable signal.

5. The multiplier circuit of claim 4 , wherein

the Booth recoded outputs further comprise a shift Booth recoded output, the shift Booth recoded output indicating whether to shift bits of the partial product left one position; and

the partial product circuit generates a value based on the multiplicand, the zero Booth recoded output and the neg Booth recoded output, and selects between the value and the neg Booth recoded output as the partial product based on the shift Booth recoded output.

6. The multiplier circuit of claim 5 , wherein

the enabling circuit ANDs the enable signal with the zero Booth recoded output prior to the partial product circuit using the zero Booth recoded output to generate the partial product, and ANDs the enable signal with the neg Booth recoded output used in the selection of the partial product.

7. A multiplier circuit, comprising:

an XOR gate exclusive ORing a multiplicand and a negative Booth recoded output, the negative Booth recoded output indicating whether to create a negative partial product;

a first AND gate ANDing a zero Booth recoded output and an enable signal, the zero Booth recoded output indicating whether to zero out the multiplicand;

a second AND gate ANDing output from the first AND gate and output from the XOR gate;

a third AND gate ANDing the negative Booth recoded output and the enable signal; and

a multiplexer selecting one of output from the second AND gate and the third AND gate as the partial product based on a shift Booth recoded output, the shift Booth recoded output indicating whether to shift bits of the partial product left one position.

8. A multiplier circuit, comprising:

an XOR gate exclusive ORing a multiplicand and a negative Booth recoded output, the negative Booth recoded output indicating whether to create a negative partial product;

a first AND gate ANDing a zero Booth recoded output and an enable signal, the zero Booth recoded output indicating whether to zero out the multiplicand;

a second AND gate ANDing output from the first AND gate and output from the XOR gate;

a multiplexer selecting one of output from the second AND gate and a carry over output from a less significant bit as the partial product based on a shift Booth recoded output, the shift Booth recoded output indicating whether to shift bits of the partial product left one position.

9. A multiplier circuit, comprising:

an XOR gate exclusive ORing a multiplicand and a negative Booth coded output, the negative Booth recoded output indicating whether to create a negative partial product;

a first AND gate ANDing a zero Booth recoded output, an enable signal and output of the XOR gate, the zero Booth recoded output indicating whether to zero out the multiplicand;

a second AND gate ANDing the negative Booth recoded output and the enable signal; and

a multiplexer selecting one of output from the first AND gate and the second AND gate as the partial product based on a shift Booth recoded output, the shift Booth recoded output indicating whether to shift bits of the partial product left one position.

10. A multiplier circuit, comprising:

an XOR gate exclusive ORing a multiplicand and a negative Booth coded output, the negative Booth recoded output indicating whether to create a negative partial product;

a first AND gate ANDing a zero Booth recoded output, an enable signal and output of the XOR gate, the zero Booth recoded output indicating whether to zero out the multiplicand;

a multiplexer selecting one of output from the first AND gate and a carry over output from a less significant bit as the partial product based on a shift Booth recoded output, the shift Booth recoded output indicating whether to shift bits of the partial product left one position.

11. A multiplier circuit, comprising:

a first AND gate ANDing a zero Booth recoded output with an enable signal, the zero Booth recoded output indicating whether to zero out a multiplicand and the enabling signal indicating whether to one of enable and disable the multiplier circuit.

12. The multiplier circuit of claim 11 , further comprising:

a second AND gate ANDing a neg Booth recoded output with the enable signal, the negative Booth recoded output indicating whether to create a negative partial product.

13. A computer implemented method of multiplying using Booth recoding, comprising:

operating a computer to generate a partial product based on outputs of the Booth recoding and a multiplicand, the generating step comprising:

ANDing the multiplicand with a zero Booth recoded output, the zero Booth recoded output indicating whether to zero out the multiplicand; and

selectively disabling the multiplying by making the zero Booth recoded output indicate to zero out the multiplicand, the selective disabling step including ANDing the zero Booth recoded output with an enable signal.

14. A simulation apparatus for simulating a multiplier circuit, comprising:

a simulated partial product circuit generating a partial product based on outputs of a simulated Booth recoder circuit and a multiplicand, the simulated partial product circuit ANDing the multiplicand with a zero Booth recoded output, the zero Booth recoded output indicating whether to zero out the multiplicand; and

a simulated enable circuit selectively enabling the simulated multiplier circuit, the simulated enable circuit disabling the simulated multiplier circuit by making the zero Booth recoded output indicate to zero out the multiplicand, wherein the simulated enabling circuit ANDs the zero Booth recoded output and an enable signal.

15. An article of manufacture taking the form of a computer readable medium for simulating a multiplier circuit having a Booth recoder circuit, the article of manufacture comprising:

a first code segment for simulating a partial product circuit that generates a partial product based on outputs of a simulated Booth recoder circuit and a multiplicand, the simulated partial product circuit ANDing the multiplicand with a zero Booth recoded output, the zero Booth recoded output indicating whether to zero out the multiplicand; and

a second code segment for simulating an enable circuit selectively enabling the simulated multiplier circuit, the simulated enable circuit disabling the simulated multiplier circuit by making the zero Booth recoded output indicate to zero out the multiplicand, wherein the simulated enabling circuit ANDs the zero Booth recoded output and an enable signal.