IP Library Granted Patent US 7,523,455
Granted Patent B2
US 7,523,455 · App. 10/139,074 · Granted Apr 21, 2009

Method and system for application managed context switching

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Quick Facts
Patent No.
US 7,523,455
App. No.
10/139,074
Granted
Apr 21, 2009
Kind
B2
Abstract

A method for application managed CPU context switching. The method includes determining whether state data of a CPU is valid for a process. The determining is performed by the process itself. If the state data of the CPU is not valid for the process, the process accesses functional hardware of the CPU to load new state data into the CPU. The process then continues to execute on the CPU using the new state data. If a context switch occurs, the existing state data of the CPU is invalidated. The state data of the CPU can be invalidated by an operating system without storing the state data in main memory.

Claims (49)

1. A computer-implemented method for application managed CPU context switching, comprising:

determining whether state data of a CPU is valid for a process, the determining performed by the process;

if the state data of the CPU is not valid for the process, accessing functional hardware of the CPU to load new state data into the CPU, the accessing performed by the process;

executing the process on the CPU using the new state data;

determining whether a context switch occurs; and

if the context switch occurs, invalidating the state data of the CPU;

wherein the invalidating the state data of the CPU, if the context switch occurs, without storing the data of the CPU.

2. The method of claim 1 further comprising:

the invalidating the state data of the CPU performed by an operating system.

3. The method of claim 1 further comprising:

determining whether the state data of the CPU is valid for the process by examining a value returned to the process from the functional hardware of the CPU, wherein the value indicates whether the state data of the CPU is valid for the process.

4. The method of claim 1 wherein the functional hardware of the CPU comprises a register table having a plurality of entries and the state data comprises the data of the plurality of entries.

5. In a process executing on a CPU of a computer system, a method for managing CPU state data after context switching, comprising:

checking whether the state data of the CPU is valid for a process, the checking performed by the process;

if the state data of the CPU is not valid for the process, accessing functional hardware of the CPU to load new state data into the CPU, the accessing performed by the process;

executing the process on the CPU using the new state data;

determining whether a second context switch occurs; and

if the second context switch occurs, invalidating the state data of the CPU;

wherein the invalidating the state data of the CPU, if the second context switch occurs, without storing the state data of the CPU.

6. The method of claim 5 further comprising:

the invalidating the state data of the CPU performed by an operating system.

7. The method of claim 5 further comprising:

after a context switch, determining whether the state data of the CPU is valid for the process by examining a value returned to the process from the functional hardware of the CPU, wherein the value indicates whether the state data of the CPU is valid for the process.

8. The method of claim 7 further comprising:

if the state data of the CPU is valid for the process, executing the process on the CPU using the state data.

9. The method of claim 5 wherein the functional hardware of the CPU comprises a register table having a plurality of entries and the state data comprises the data of the plurality of entries.

10. A computer-readable media having computer readable code which when executing by a computer system cause the computer system to implement a method for managing CPU state data on a per process basis, comprising:

checking whether state data of a CPU is valid for a process, the checking performed by the process;

if the state data of the CPU is not valid for the process, accessing functional hardware of the CPU to load new state data into the CPU, the accessing performed by the process;

executing the process on the CPU using the new state data;

checking whether a context switch occurs; and

if the context switch occurs, invalidating the state data of the CPU;

wherein the invalidating the state data of the CPU, if the context switch occurs, without storing the data of the CPU.

11. The media of claim 10 further comprising:

discarding the state data of the CPU, the discarding performed by an operating system.

12. The media of claim 10 further comprising:

determining whether the state data of the CPU is valid for the process by examining a value returned to the process from the functional hardware of the CPU, wherein the value indicates whether the state data of the CPU is valid for the process.

13. A system for managing CPU state data on a per process basis, comprising:

a CPU;

within a process executing on the CPU, means for determining whether state data of the CPU is valid for the process;

means for accessing functional hardware of the CPU to load new state data into the CPU, if the state data for the process of the CPU is not valid for the process;

means for executing the process on the CPU using the new state data;

means for determining whether a context switch occurs; and

if the context switch occurs, means for invalidating the state data of the CPU;

wherein the means for invalidating the state data of the CPU, if the context switch occurs, without storing the data of the CPU.

14. The system of claim 13 further comprising:

means for invalidating the state data of the CPU using an operating system.

15. The system of claim 13 further comprising:

means for determining whether the state data of the CPU is valid for the process by examining a value returned to the process from the functional hardware of the CPU, wherein the value indicates whether the state data of the CPU is valid for the process.

Assignments (3)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Nov 18, 2021
From: OT PATENT ESCROW, LLC
To: VALTRUS INNOVATIONS LIMITED
Reel/Frame 058897/0262 →
PATENT ASSIGNMENT, SECURITY INTEREST, AND LIEN AGREEMENT Recorded Jan 26, 2021
From: HEWLETT PACKARD ENTERPRISE DEVELOPMENT LP; HEWLETT PACKARD ENTERPRISE COMPANY
To: OT PATENT ESCROW, LLC
Reel/Frame 055269/0001 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Nov 9, 2015
From: HEWLETT-PACKARD DEVELOPMENT COMPANY, L.P.
To: HEWLETT PACKARD ENTERPRISE DEVELOPMENT LP
Reel/Frame 037079/0001 →