IP Library Granted Patent US 7,185,036
Granted Patent B1
US 7,185,036 · App. 10/139,654 · Granted Feb 27, 2007

Look up table based upsampling and digital filtering

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Quick Facts
Patent No.
US 7,185,036
App. No.
10/139,654
Granted
Feb 27, 2007
Kind
B1
Abstract

A system and method are disclosed for processing a signal that includes receiving encoded data including a plurality of input symbols; generating an input symbol set from the plurality of input symbols; looking up a plurality of output samples for the input symbol set; and outputting the plurality of output samples.

Claims (36)

1. A method of processing a signal including: receiving encoded data including a plurality of input symbols; generating an input symbol set from the plurality of input symbols; looking up a plurality of output samples that correspond to a plurality of interpolated values of the input symbol set; and outputting the plurality of time shifted output samples; wherein looking up the plurality of output samples includes: finding the outputs in a plurality of lookup tables (LUTs); and selecting an appropriate LUT for a given output sample using a multiplexer.

2. A method of processing a signal as recited in claim 1 wherein the input symbol set includes six symbols.

3. A method of processing a signal as recited in claim 1 wherein looking up the plurality of output samples includes finding the outputs in a LUT having a plurality of entries and wherein the plurality of entries in the LUT correspond to time shifted output samples.

4. A method of processing a signal as recited in claim 1 wherein generating the input symbol set from the plurality of input symbols includes storing the input symbol set in a memory device.

5. A method of processing a signal as recited in claim 1 generating the input symbol set from the plurality of input symbols includes storing the input symbol set in a memory device and wherein looking up the plurality of output samples includes finding the outputs in a LUT.

6. A method of processing a signal as recited in claim 1 wherein the plurality of input symbol sets are split into I and Q components and the I and Q components are used as inputs to separate LUTs to obtain the plurality of output samples.

7. A method of processing a signal as recited in claim 1 wherein the plurality of output samples comprise a band limited signal.

8. A method of processing a signal as recited in claim 1 wherein looking up the plurality of output samples includes finding the outputs in a LUT and wherein the LUT includes a beginning section and an ending section.

9. A method of processing a signal as recited in claim 1 wherein looking up the plurality of output samples includes finding the outputs in a LUT and wherein the LUT includes a beginning section, a middle section and an ending section.

10. A method of processing a signal as recited in claim 1 wherein looking up the plurality of output samples includes finding the outputs in a LUT and wherein the LUT is compressed.

11. A method of processing a signal as recited in claim 1 wherein looking up the plurality of output samples includes finding the outputs in a LUT and wherein the LUT excludes certain potential input sets.

12. A method of processing a signal as recited in claim 1 wherein the plurality of LUTs are used in conjunction with a state counter.

13. A method of processing a signal as recited in claim 1 wherein looking up the plurality of output samples includes:

finding possible output samples in a plurality of LUTs using a first state counter; and

selecting the output samples from the possible output samples using a multiplexer and a second state counter.

14. A method of processing a signal as recited in claim 1 , further comprising encoding a plurality of inputs to generate the encoded data.

15. A method of processing a signal as recited in claim 1 wherein the plurality of input symbols has a lower clock rate than the plurality of output samples.

16. A method of processing a signal including: receiving encoded data including a plurality of input symbols; generating an input symbol set from the plurality of input symbols; looking up a plurality of output samples that correspond to a plurality of interpolated values of the input symbol set; and outputting the plurality of time shifted output samples; wherein looking up the plurality of output samples includes finding the outputs in a plurality of lookup tables (LUTs) each having a plurality of entries and wherein the plurality of entries in each of the plurality of LUTs corresponds to interleaved output samples.

17. A system for processing a signal including: an input for receiving encoded data including a plurality of input symbols; symbols; a first memory for storing an input symbol set derived from the plurality of input a second memory configured to store a plurality of interpolated time shifted output samples; wherein the plurality of time shifted output samples are obtained by looking up the input symbol set; and wherein the second memory includes a plurality of lookup tables (LUTs) having a plurality of LUT outputs, and a multiplexer configured to select one of the plurality LUT outputs.

18. A system for processing a signal as recited in claim 17 wherein the input symbol set includes six symbols.

19. A system for processing a signal as recited in claim 17 wherein the second memory includes a LUT having a plurality of entries and wherein the plurality of entries in the LUT correspond to time shifted output samples.

20. A system for processing a signal as recited in claim 17 wherein the first memory includes a shift register.

21. A system for processing a signal as recited in claim 17 wherein the first memory includes a shift register and the second memory includes a LUT.

22. A system for processing a signal as recited in claim 17 wherein the selected one of the plurality of outputs results in a band limited signal.

23. A system for processing a signal as recited in claim 17 wherein the second memory includes a LUT and wherein the LUT includes a beginning section and an ending section.

24. A system for processing a signal as recited in claim 17 wherein the second memory includes a LUT and the LUT includes a beginning section, a middle section and an ending section.

25. A system for processing a signal as recited in claim 17 wherein the second memory includes a LUT and wherein the LUT is compressed.

26. A system for processing a signal as recited in claim 17 wherein the second memory includes a LUT and wherein the LUT excludes certain potential input sets.

27. A system for processing a signal as recited in claim 17 wherein the plurality of LUTs are used in conjunction with a state counter.

28. A system for processing a signal as recited in claim 17 wherein the second memory includes:

a plurality of LUTs having a first state counter for selecting outputs from the plurality of LUTs;

a multiplexer for selecting one of the plurality of LUTs using a second state counter.

29. A system for processing a signal as recited in claim 17 wherein the input symbol set includes I and Q components and wherein the second memory is configured to store a plurality of outputs for possible I and Q components of the input symbol set and wherein the second memory is configured to output selected I and Q component outputs that correspond to the I and Q components of the input symbol set.

30. A system for processing a signal as recited in claim 17 further comprising a processor configured to encode a plurality of inputs to generate the encoded data.

31. A system for processing a signal as recited in claim 17 wherein the plurality of input symbols has a lower clock rate than the plurality of output samples.

32. A system for processing a signal including: an input for receiving encoded data including a plurality of input symbols; a first memory for storing an input symbol set derived from the plurality of input symbols; a second memory configured to store a plurality of interpolated output samples; wherein the plurality of time shifted output samples are obtained by looking up the input symbol set; and wherein the second memory includes a plurality of lookup tables (LUTs) and wherein the entries in each of the plurality of LUTs corresponds to interleaved output samples.

Assignments (2)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Nov 20, 2012
From: QUALCOMM ATHEROS, INC.
To: QUALCOMM INCORPORATED
Reel/Frame 029328/0052 →
MERGER Recorded Jul 15, 2011
From: ATHEROS COMMUNICATIONS, INC.
To: QUALCOMM ATHEROS, INC.
Reel/Frame 026599/0360 →