Method and system for single-chip camera
View Patent ↗Method and system for a single-chip camera where an image sensor is a single-chip digital color imaging device that incorporates a sensor array that captures still or full-motion video and converts the images to digital data. Moreover, the image sensor employs a built-in correlated double sampler, an internal analog-to-digital converter, and a timing circuitry. Output from the sensor is an 8-bit or more raw data, horizontal sync signals, and vertical sync signals. The output raw data may then be fed into a compression circuit that generates packets of compressed output data. The compressed data is transmitted with a USB transceiver using isochronous packets. The packets are then received, decompressed, and color processed by a host PC.
1. A single-chip integrated circuit camera system, comprising:
an image sensor;
one or more external optical elements for focusing light onto the surface of the image sensor;
an image-processing element for receiving raw image data and timing signals from the image sensor;
a data storage element for storing image data produced by the image-processing element;
a communication interface element for controlling input and output data and control signals for the camera;
an on-chip multiplexer;
a register set; and
a test access element for verifying camera internal functionality, said test access element comprises one or more IO pins, wherein the one or more IO pins is either connected to the register set for controlling external functions or connected to internal data inputs and outputs for testing purpose, wherein the connection of the one or more IO pins is controlled by the on-chip multiplexer,
wherein said image sensor, said image-processing element, said data storage element, said communication interface, said on-chip multiplexer, said register set and said test access element are on said single chip integrated circuit camera.
2. The camera system of claim 1 , wherein the image sensor comprises a sensor array.
3. The camera system of claim 2 , wherein the image sensor further comprises a built-in correlated double sampler.
4. The camera system of claim 3 , wherein the image sensor further comprises an internal analog-to-digital converter.
5. The camera system of claim 4 , wherein the image sensor further comprising a timing circuitry.
6. The method of claim 5 , wherein the output data is generated as an 8-bit raw data, a horizontal sync signal, and a vertical sync signal.
7. The method of claim 5 , wherein the output data is generated as an 10-bit raw data, a horizontal sync signal, and a vertical sync signal.
8. The method of claim 5 , wherein the output data is generated as a 12-bit raw data, a horizontal sync signal, and a vertical sync signal.
9. The camera system of claim 1 , wherein the image-processing element comprises an element for image rendering or enhancement.
10. The camera system of claim 1 , wherein the image-processing element comprises an element for image recognition.
11. The camera system of claim 1 , wherein the image-processing element comprises an element for image compression.
12. The camera system of claim 1 , wherein the image-processing element is implemented with specific hardware accelerated circuits.
13. The camera system of claim 1 , wherein the image-processing element is implemented with embedded microprocessor firmware.
14. The camera system of claim 1 , wherein the data storage element comprises a static random access memory.
15. The camera system of claim 1 , wherein the data storage element comprises a dynamic random access memory.
16. The camera system of claim 1 , wherein the data storage element comprises a non-volatile memory.
17. The camera system of claim 1 , wherein the communication interface element comprises an interface to a control or transmission interface.
18. The camera system of claim 1 , wherein the communication interface element comprises an interface to a memory interface.
19. The camera system of claim 1 , wherein the communication interface element comprises an interface to a display interface.
20. The camera system of claim 1 , wherein the communication interface element comprises an interface to an audio interface.
21. The camera system of claim 1 , further comprising a power-monitoring block for shutting down all activities on the single-chip camera during a low power state.
22. The camera system of claim 1 , further comprising a set of one or more control registers.
23. The camera system of claim 22 , further comprising a register control logic element for translating control data to and from the one or more control registers.
24. The camera system of claim 23 , further comprising a serial decoder for translating high speed requests from the communication interface element into lower speed requests for the image sensor.
25. The camera system of claim 1 , wherein each element of the camera is categorized as analog or digital.
26. The camera system of claim 25 , wherein electrical activity is separated between analog elements and digital elements.
27. A method for a single-chip integrated circuit camera, comprising the steps of:
exposing one or more lines of pixels of a sensor array to light;
sampling the one or more lines of pixels with an analog-to-digital converter;
applying a correlated double sampling using a image processing element to the sampled pixels to eliminate point-wise fixed pattern noise;
adjusting digital gain to preserve color fidelity using said image processing element;
sending resulting data to an output control element; and
testing internal functionality of the single-chip integrated circuit camera using a test access element comprising one or more IO pins, wherein the one or more IO pins is either connected to a register set for controlling external functions or connected to internal data inputs and outputs for testing purpose, wherein the connection of the one or more IO pins is controlled by an on-chip multiplexer,
wherein said image sensor, said analog-to-digital converter, said image processing element, said output control element, said test access element, said register set and said on-chip multiplexer, are on said single chip integrated circuit camera.
28. The method of claim 27 , further comprising the step of compressing the data from the output control element.
29. The method of claim 28 , wherein the compressing step comprises: compressing the data with a differential coding, compressing the resulting compressed data with Huffman coding, and loading the resulting compressed data into packets.
30. The method of claim 28 , wherein the compressing step comprises: compressing the data with JPEG coding and loading the resulting compressed data into packets.
31. The method of claim 28 , wherein the compressing step comprises: compressing the data with MPEG coding and loading the resulting compressed data into packets.
32. The method of claim 28 , wherein the compressing step comprises: compressing the data with a wavelet coding and loading the resulting compressed data into packets.
33. The method of claim 28 , further comprising the step of sending the compressed data via an interface to a host computer wherein said interface is on said single chip integrated circuit camera.
34. The method of claim 33 , wherein the interface is an USB interface controller.
35. The method of claim 33 , wherein the interface is an IEEE 1394 interface controller.
36. The method of claim 33 , wherein the interface is a hardwired LAN interface controller.
37. The method of claim 33 , wherein the interface is a Bluetooth wireless interface controller.
38. The method of claim 33 , wherein the interface is a wireless LAN interface controller.