Method/apparatus for conversion of higher order bits of 64-bit integer to floating point using 53-bit adder hardware
View Patent ↗A floating point unit capable of converting a 64-bit integer number to a floating point format is provided. The floating point unit includes an 11-bit zero/one complement detect circuitry in an exponent datapath of the floating point unit, where the 11-bit zero/one complement detect circuitry is used to determine a shift count for a right shifter in a large exponent difference mantissa datapath of the floating point unit. The 11-bit zero/one complement detect circuitry determines shift counts based on particular bit groupings of the 64-bit operand.
1. An integrated circuit, comprising:
a floating point unit arranged to receive a first operand having an integer value and to output a floating point value, the floating point unit comprising:
a small exponent difference datapath arranged to receive a first portion of the first operand,
a large exponent difference datapath arranged to receive the first portion of the first operand, and
an exponent datapath arranged to receive a second portion of the first operand, the exponent datapath comprising n-bit zero/one complement detect circuitry that is used to determine a shift count based on an n-bit group in the first operand,
wherein the large exponent difference datapath outputs a portion of the floating point value dependent on the shift count.
2. The integrated circuit of claim 1 , the large exponent difference datapath comprising a right shifter, wherein the large exponent difference datapath is arranged to receive the shift count, wherein the shift count is used by the large exponent difference datapath to determine how many bit places the right shifter is to be shifted.
3. The integrated circuit of claim 1 , further comprising:
circuitry that multiplexes the shift count and a normal mode value, wherein an output of the circuitry is used to selectively merge register data in the right shifter.
4. The integrated circuit of claim 1 , wherein a register containing the value of the first operand is formatted and merged dependent on the shift count to yield the portion of the floating point value.
5. An integrated circuit, comprising:
adder means for receiving a first operand having an integer value and outputting a floating point value, the adder means comprising:
first datapath means for receiving a first portion of the first operand,
second datapath means for receiving the first portion of the first operand, and
exponent datapath means for receiving a n-bit portion of the first operand, the exponent datapath means comprising n-bit zero/one complement detect circuitry that is used to determine a shift count based on the n-bit portion,
wherein the second datapath means outputs a portion of the floating point value dependent on the shift count.
6. An integrated circuit, comprising:
a 64-bit floating point adder arranged to receive a 64-bit operand, the 64-bit floating point adder comprising:
a small exponent difference datapath arranged to receive a 52-bit portion of the 64-bit operand,
a large exponent difference datapath arranged to receive a 53-bit portion of the 64-bit operand, and
an exponent datapath arranged to receive an 11-bit portion of the 64-bit operand, the exponent datapath comprising 11-bit zero/one complement detect circuitry that is used to output a shift count based on the 11-bit portion,
wherein the large exponent difference datapath outputs a portion of a 64-bit output from the 64-bit floating point adder dependent on the shift count.
7. The integrated circuit of claim 6 , the large exponent difference datapath comprising a 64-bit right shifter, wherein the large exponent difference datapath is arranged to receive the shift count, wherein the shift count is used by the large exponent difference datapath to determine how many bit places the 64-bit right shifter is to be shifted.