Power reduction mechanism for floating point register file reads
View Patent ↗A system and method for reducing power consumed by a floating unit performing iterative calculations in a loop through selectively inhibiting floating point register file reads. One or more source register address values are compared with one or more current values generated from a first iteration of a loop, and upon determining that one ore or more values in the source registers are the same as one or more current generated values, floating point register file reads of the equal values from the one or more source registers are inhibited. The current generated values from the first iteration of the loop are preferably held in one or more pipeline registers.
1. A system for reducing floating point register file
reads during an iterative loop on a processor, comprising:
a processor including a floating point unit having a floating point register, and a source register, the processor capable of selectively executing iterative loops;
a pipeline register that holds a current value generated in the iterative loop; and
a register read monitor that compares a source register value with the current value and that inhibits a floating point register file read from the source register upon determining that the source register value is the same as the current value,
wherein the processor uses the current value in the pipeline register for a next iteration of the iterative loop upon determining that the value in the source register is the same as the current value in the pipeline register.
2. The system of claim 1 , wherein the register read monitor compares two source register values with two current values generated from one iteration of a loop, and upon determining that one or both values in the source registers are the same as one or both of the current generated value, the monitor inhibits a floating point register file read of one or both of the equal values from one or both of the source registers.
3. A method for reducing floating point register file reads during an iterative loop on a processor including a floating point unit having a floating point register, and a source register, the processor selectively executing iterative loops, the method comprising the steps of:
obtaining a source operand from the source register;
performing a first calculation of an iterative loop on the obtained source operand to generate a current value;
comparing the source operand with the current value generated from one iteration of a loop;
selectively inhibiting a floating point register file read from the source register prior to an iteration of the loop upon determining that the value of the source operand is the same as the current value;
storing the current value generated in the iterative loop in a pipeline register; and
using the current value in the pipeline resister for the second calculation of the iterative loop after inhibiting a floating point register file read from the source register.
4. The method of claim 3 , wherein:
the step of comparing the source operand includes comparing two source register values with two current values generated from one iteration of a loop; and
the step of inhibiting a floating point register file read upon determining that the two source register values are the same as one or both the two current values generated from one iteration of a loop includes inhibiting a floating point register file read of one or both of the values from one or both of the source registers.